DMAC Setting that allows transfers to be repeated without instruction from CPU.

[JuIn_1625121]

The customer wants to use DMA transfer with these settings.

DMACB:
EM=1 (Dose not clear DMACA:EB bit (bit31) upon completion of the transfer.)
RC=1 (Enables the reload function of BC/TC.)
RS=1（Enables the reload function of the transfer source address.)
RD=0 (Enables the reload function of the transfer destination address.)

Can he set?

There is the description on the manual.
"This function can only be used for hardware transfer. To use the function, enable the reload function of RC, RS and
RD bits."
Is it a rule that must be obeyed?

Best regards,

Inoue

[AchimE_41 · Accepted solution]

Hi Inoue,

what is the use case of disabling the reload of the destination address?

To my understanding it makes no sense to disable it, as the address will always be incremented (assuming FD=0, otherwise the reloaded doesn't do any harm) until it hits a forbidden address and generates a hard fault.

kind regards,

Achim

[JuIn_1625121]

Hi Achim,

Thank you for your answer.

For example

1) For 10 transfers, store them in the buffer without reloading

2) Update the address by software in the 10th → 11th time

The customer assumes the above usage. Is this usage permitted?

In this case, the customer assumes that it will not hit the forbidden address.

Best Regards,

Inoue

[AchimE_41]

Hi Inoue,

Technically it should be possible, but I would not recommend it due to above concerns.

What happens if the trigger at the 10th data transfer is missed or delayed for whatever reason?

I think it is better to use the transfer counter (TC) and Reload the destination address to limit the memory area accessed by the DMA.

As this forms a ring buffer, you have to store the the address where you stopped reading from the buffer to know where to continue with the next read.

kind regards,

Achim