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By Interrupt of MFS, can be DMA transfer that is Hardware-Block transfer or Hardware-Burst transfer used?
If yes, How to use it?
Best Regards,
Inoue
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Hi Inoue,
Yes, to My understanding this is possible. As the DMAC is triggered by the MFS interrupt signals following configuration should be used:
- The MFS receive interrupt has to be configured for triggering at a certain FIFO level using the FBYTE register.
- The MFS transmit interrupts has to be configured for FIFO empty signals, in case automated sensing is required, too.
Of course there might be some data left in the RX FIFO when processing it and the level defined in FBYTE was not reached, this has to be considered.
kind regards,
Achim
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Hi Inoue,
Please have a look at following example: http://www.cypress.com/documentation/software-and-drivers/mb9bfxxx-mfs4-dma-timeout-v10
This should be a good reference to solve your problem.
It implements MFS4 that stores its data on reception in a RAM buffer via DMA.
There is also a second DMA channel used to reset a timer on reception to prevent a timeout.
I hope this helps,
Achim
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Hi Achim,
Thank you for your answer.
I think the reference is used interrupt of Base timer and Demand transfer.
Does your answer mean that the there is no problem setting the interrupt source to MFS and the transfer to hardware - block transfer or hardware - burst transfer by referring to this document?
Best Regards,
Inoue
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Hi Inoue,
Yes, to My understanding this is possible. As the DMAC is triggered by the MFS interrupt signals following configuration should be used:
- The MFS receive interrupt has to be configured for triggering at a certain FIFO level using the FBYTE register.
- The MFS transmit interrupts has to be configured for FIFO empty signals, in case automated sensing is required, too.
Of course there might be some data left in the RX FIFO when processing it and the level defined in FBYTE was not reached, this has to be considered.
kind regards,
Achim