CY62126ESL Latch up

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Anonymous
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Good day, I use 2 CY62126ESL, for the organization of 32-bit mode.

When reading from the memory cells of both chips simultaneously (32-bit mode), when the number of units in the data exceeds 70%, there is an effect of Latch up. There is a current surge up to 12A. Is this a normal mode of operation? How to overcome such a release?

Добрый день, я использую 2 CY62126ESL, для организации 32 -битного режима.

При чтении из ячеек памяти обеих микросхем одновременно (32-битный режим), когда количество единиц в данных превышает 70%, наблюдается эффект Latch up. Наблюдается бросок тока до 12А. Является ли это нормальным режимом работы? Как побороть такой выброс?

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3 Replies
PradiptaB_11
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500 replies posted 250 solutions authored 250 replies posted

Hi White,

Can you please provide us with the schematics of the SRAM portion for your application.

Thanks,

Pradipta.

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Anonymous
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1 Set the address to ADDR / DAT_2-17

2 DD4 and DD5 Latches hold the address and feed it to DS1 and DS2

3 Remove the address ADDR/DAT_2-17

4 DD4 and DD5 Latches continue to hold the address and feed it to DS1 and DS2

5 give the command to read DS1 and DS2, at the address that holds DD4 and DD5

6 If the number of " 1 " in the data exceeds ~70%, the effect of Latch up is observed. There is a current surge up to 12A

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SudheeshK
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250 sign-ins First question asked 750 replies posted

Hi White Leo,

We are not aware of any such issues with our devices (consuming a high current (12A) during read operation). We would like to get some more details about this issue?

1. Are you observing this issue with all of the boards that you tested? Or, is it with only one board?

2. If it is with only one board, can you replace the SRAMs on that board with new ones and check if the issue happen again?

3. Are the IO lines shared between any other devices?

4. Are you observing such high current consumption during write operation also?

Thanks and Regards,

Sudheesh

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