S25FL256L Quad Page Program issue

[Anonymous]

Hello everyone, this is my first post in the community.

We're trying to use the new S25FL256L flash as Xilinx FPGA boot up memory. This L version is not officially supported by Xilinx (S or P version should OK but all EOL). According to Cypress application notes we can use old Xilinx iMPACT tool and modify the environment parameter to bypass the ID check. However, iMPACT (old version) is not supporting the new Artix-7 XC7A50T. So we end-up have to write our own programming code. During the development it's found that S25FL256L can't accept Quad Page Program command QPP32h. All data after the 32h and address bits sent through SPI weren't written into the flash. Read back is all "FFh" since erase was successfully. If we change the command to PP02h single line write, it works fine. We can read ID 016019 from the chip so assume circuit is OK.

Does anyone experience similar issue? Any idea where could be wrong? Thanks in advance.

Regards,

Weber

[VincentH_06 · Accepted solution]

Hi Weber,

The FL256L is default in SPI mode, if you want to use the Quad-SPI mode, you should config the CR1V[1] (config for every power on) or CR1NV[1] (config only for 1 time) to enable the Quad-SPI mode.

Please refer the section 6.6.3 of the datasheet for more information:

Vincent Han

Customer Application Engineer, Cypress

[Anonymous]

Hi Vhan,

Thank you so much. You're right, the flash must be configured to QUAD mode (WRR to CR1NV). Not only it enables quad write in page, most importantly it enables Xilinx FPGA to load configuration in SPIx4 mode at power up.

Regards,

Weber