Hi,
I am using Quartus and Arria 10 in my design. I want to have USB3.0 functionality in the design so I modified the slavesyncFIFO example provided. Instead of a loopback, the data is just read into a FIFO from the GPIF II interface. From here, the external controller can access it and POP values when available. However, my problem arises between compiles of my project. I verified that with only the HPS and FX3 files included in my project, the Read works properly. However, when I add the other peripherals in my design, I receive either 1 or 2 extra bytes. Usually the extra byte(s) are read at the end. I can see the extra byte occurs in the FIFO buffer when using SignalTap II. The extra byte is usually just a zero. Due to the change in the amount of extra byte between compiles of my project, I am led to believe that it is a timing issue. I found a couple when Googling about FX3 timing, but none of them answered input timing. There is also an included SDC file in the example project, but it only includes output and not input delay. What values should I use for the input delay?
Also, after adding some timing constraints, I found that the extra byte was no longer zero, but seemed to either be 01, 10, or 00 depending on the last Byte value sent. I am let further by this to think it is a timing problem.
Thank you
