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I have used the PSoC Sensei FIFOin component, but cannot find a FIFOout version. Can anyone point me in the right direction or share something like this?
It is very frustrating that these components are still not included with PSoC creator. After a few hours reading about the UDB editor and datapath, I realize that creating my own version is not a simple task. Getting data to the PLD section should not be the hardest part of my design!
Thanks for reading
Solved! Go to Solution.
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There is no FIFOout component , If your requirement is a parallel output of FIFO content, this is not possible with directly with UDBs however you can have a parallel output of the accumulator from the default instance of the datapath, you should instantiate cy_psoc3_dp while selecting the datapath.
And if you are planning to use DMAs you can transfer content to FIFO, push it into Accumulator in one of the state of datapath , the output will be driven on the parallel output.
I'm attaching a component that I developed some time back with 16bit parallel output of a counter .Please note that this is just for your reference and may not be production ready.
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There is no FIFOout component. I understand frustration starting UDB design. Typically parallel input is not required for UDB. Can you describe what you trying to accomplish to further advise you?
odissey1
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The goal is to transfer good size blocks of data back and forth with an FPGA.
The first thing I noticed was the external memory interface components. They seemed ideal until I noticed their bus clock maximum is 33Mhz.
Since there is great flexibility on the FPGA side, I decided I could "roll my own" interface. This would avoid dragging down the whole bus clock and possibly messing with the clocks to my other modules. I thought 16 bit FIFOin and FIFOout with DMA and a bit of glue logic would be the solution. Unfortunately, I didn't realized the scope of getting a working FIFOout.
Then I thought 8 bit FIFOin and 8 bit control register out with DMA might be adequate. The DMA would be less efficient, but would probably still get the job done. In this scenario, I don't know when the control register is updated with a new byte, so I can't get a usable write signal to the FPGA.
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I second your sentiment. I've worked really hard on a few PSOC projects to get around the lack of goof fifo support form GPP to FPGA and back.
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There is no FIFOout component , If your requirement is a parallel output of FIFO content, this is not possible with directly with UDBs however you can have a parallel output of the accumulator from the default instance of the datapath, you should instantiate cy_psoc3_dp while selecting the datapath.
And if you are planning to use DMAs you can transfer content to FIFO, push it into Accumulator in one of the state of datapath , the output will be driven on the parallel output.
I'm attaching a component that I developed some time back with 16bit parallel output of a counter .Please note that this is just for your reference and may not be production ready.
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Thanks for the advice.
For a simple start I thought I could write to A0 from the CPU and output on PO. So far I am am having no success.
Looking at the datapath block diagram, it appears that PO could be sourced by A0 or A1.
Is there a setting in the Datapath Configuration Tool that connects PO to A0 or A1?
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Its in the output port declaration of the generic datapath instance .Please check the example attached in the previous response.
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I fixed some errors and got A0 to PO data flowing. I still don't understand why PO is connected to A0 (vs. A1 or open). I have moved on regardless and got the F0 to A0 load working. A little more work on status and control bits should yield a usable component.
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Great component! Thank you for sharing with community.
odissey1
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Hi,
I am testing the FIFOout component. Can you confirm that it takes 3 input clocks to push one data value out of a FIFO?
Thank you again for sharing the component.
/odissey1
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Sorry I missed your posts. I don't know how this forum works. Normally there is a "subscribe" to get emails on post activity and you always get subscribed to your own. Anyway, I hope you got it working, because I really don't remember the details of that project.
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Thank you again for sharing the code. I tested the component and studied its internals, but didn't use it in any project so far. You can get email notifications by modifying settings in your profile.
/odissey1