UDB: generate ready signal when arithmetic/logic function finishes

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi,

perhaps a dumb question:

I'm modifying the parallel in/out example from AN82156 to have an UDB based adder with two parallel 8-bit inputs and carry in/out. This should be no problem, but I also need an operation result ready signal. How to generate this?

The current implementation has only two states: the idle state(1b0), which loads PI to A1, and the add state (1b1, forced by a rising edge on a trigger input), which adds the PI/A0 value to A1 and outputs the ALU result to PO. Now, how to generate the ready signal? If I use the state value as a ready signal, I think it's rising too early, because the datapath needs some time. Or should the ready signal equal to the inversion of the state bit, so that the ready state is signalled when the state machine is in idle state?

Regards

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1 Solution
JobinT_31
Employee
Employee
50 solutions authored 25 solutions authored 10 solutions authored

Hello,

I believe you can use the state signal changing 1 to 0 as a ready signal.

Thanks

Jobin GT

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3 Replies
JobinT_31
Employee
Employee
50 solutions authored 25 solutions authored 10 solutions authored

Hello,

I believe you can use the state signal changing 1 to 0 as a ready signal.

Thanks

Jobin GT

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Hello Jobin,

thank you for your answer, it works to have the ready signal extracted out of the state signal. However, I have to revert my statement that it should be no problem to get the adder to work It seems that I can't get the routed carry input to work properly.

CI_SELA is set to ROUTE, and in the verilog file the .CI_ROUTE input is set to a registered carry input signal of the module. The carry input is registered when the state machine is instructed to run. Any ideas what's going wrong?

Regards

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Can you post the component?

/odissey1

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