PSoC 5LP using 2 SAR ADCs to get 2MSPS?

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MaWo_1214996
Level 3
Level 3
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Hello,

is it possible to use 2 SAR ADCs interleave to get 2 MSPS by supplying an external clock accordingly and assemble the signal after that again?

Anyone ever tried this?

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Yes, it is possible. Look at this post by 'kabron'

ADC SAR Overclocking Technique

What is  important, is that interleaving of two 12-bit 1 MHz ADCs is unlikely to yield a 12-bit result at 2 MHz due to their gain/offset mismatch. Is speed gain of 2 worth the hassle?  

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Yes, it is possible. Look at this post by 'kabron'

ADC SAR Overclocking Technique

What is  important, is that interleaving of two 12-bit 1 MHz ADCs is unlikely to yield a 12-bit result at 2 MHz due to their gain/offset mismatch. Is speed gain of 2 worth the hassle?  

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

One possible way to interleave two SAR_ADC is to collect sequential ADC data into FIFO buffer using custom component FIFOin by Brad Budlong (AKA 'PSoC Sensei'). Attached below is (non-working) demo stub, exemplifying this approach (not tested). It uses standard ADC_SAR customized with hardware output bus. For simplicity the bus width is set to 8-bit, but 10- and 12-bit allowed as well. This bus is de-multiplexed using a HardwareMux and feed into the 4-samples deep FIFO buffer. Once FIFOin is filled with data, it can be transferred to RAM using DMA (not shown). To operate ADC in interleaved fashion, they are hardware triggered on opposite edges of the clock divider. The analog clock settings, divider, bus clock, etc. need to be tuned-up to get to 1 MHz sampling speed for each ADC. As shown by 'Kabron' in the above link, it is possible overclock SAR_ADC up to 1.9 MHz each.

Attached are project file and associated libraries (ADC_SAR_ex and FIFOin), which must be installed using Project->Dependencies->User Dependencies.

SAR_ADC_x2_01a.png.png

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Thank you, I will look into it.

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Another (easy solution) can be DMA transfer ADC_1 and ADC_2 data to the same intermediate fixed location in RAM using two DMAs (one for each ADC), and then moving it out to the buffer destination array using 3-rd DMA channel. It believe that it should work for 1MHz each ADC, but that is probably the max.

/odissey1

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