clk_bus slower than counter clock- Is it possible?

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Anonymous
Not applicable

I would like to use counter in PSOC5 with clock frequency of 80MHz in order to measure event accuratlly.

At the same time I would like to operate the CPU (and all the other peripherials) with 10 or 20MHz clock in order to save power.

Is it possible?

thanks

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1 Solution

CPU clock can run at lower clock than UDB clock.

As UDB clock is synchronized with Master clk and Bus_clk (CPU Clock) is obtained by dividing the Master clock in .cydwr.

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4 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

A look into the counter datasheet, AC specs show that for the FF implementation the max frequency is 67 MHz.

The explanation of th clock input shows that for the UDB implementation the clock input is used for detecting changes of the count input.

Bob

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Anonymous
Not applicable

Can I use a counter (fixed function or UDB)  in PSOC5 with clock frequency of 60MHz while at the same time  the CPU (and all the other peripherials) run with 10 MHz clock ?(in order to save power).

thanks

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The UDB runs on bus clock. I believe that is is not possible to run CPU slower than UDB.

/odissey1

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CPU clock can run at lower clock than UDB clock.

As UDB clock is synchronized with Master clk and Bus_clk (CPU Clock) is obtained by dividing the Master clock in .cydwr.

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