PSOC 5lp BPM Interrupt Question

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cross mob
Anonymous
Not applicable

Hey guys,

I am working on a project where the PSOC 5LP will generate an accurate interrupt in beat with some music. I am struggling with generating a consistent interrupt that will not stray with time... Inside the interrupt handler will be some code to control some motors

So far I am using a timer connected to a 12MHz PLL clock to generate the interrupt on overflow. The timer is set on continuous with a UDB implementation (fixed does not have resolution big enough to handle slower BPMs)

I am also struggling with altering the period of the timer dynamically... I have tried this:

period = (60*CLOCK_BPM_FREQ)/BPM //  CLOCK_BPM_FREQ is the frequency of the timers clock (12000000) and BPM periodically.

timer_BPM_WritePeriod(period);

timer_BPM_WriteCounter(0);

Any ideas on how to solve these problems would be much appreciated!!

Happy Holidays

Stefan

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1 Solution
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

I recommend using DDS component for generating frequency instead of Timer. The difference is that it updates frequency instantly and provides uniform frequency accuracy across the entire range. You can find different versions DDS24 and DDS32 (draft version) here:

DDS24: 24-bit DDS arbitrary frequency generator component

Re: How can I handle a PSoC 5 community library DDS24 on PSoC 4 BLE device ? 

The difference in implementation and features (24-bit vs. 32-bit; PLD vs UDB, hardware bus output / no bus; etc.).

Re: PSOC with verilog, how big a design can one make?

/odissey1

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1 Reply
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

I recommend using DDS component for generating frequency instead of Timer. The difference is that it updates frequency instantly and provides uniform frequency accuracy across the entire range. You can find different versions DDS24 and DDS32 (draft version) here:

DDS24: 24-bit DDS arbitrary frequency generator component

Re: How can I handle a PSoC 5 community library DDS24 on PSoC 4 BLE device ? 

The difference in implementation and features (24-bit vs. 32-bit; PLD vs UDB, hardware bus output / no bus; etc.).

Re: PSOC with verilog, how big a design can one make?

/odissey1

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