PSOC 6 SMIF XIP question

[NiLi_2861801]

Hello, I use CY8CKIT-062-BLE to test the SMIF XIP mode.

The addresss mapped to 0x18000000u, the size is 0x04000000. and I also set up the write enable bit.

Then，I can read these memory. But I cannot modify the value like this,  *(int *)(0x18000000u) = 0x55.  How can I do ?

Here is the code:

   /* SMIF IP initialization */

    Cy_SMIF_Init(SMIF_FLASH_HW, &SMIF_FLASH_config, 200, &SMIF_FLASH_context);

    Cy_SMIF_SetDataSelect(SMIF_FLASH_HW, CY_SMIF_SLAVE_SELECT_0, CY_SMIF_DATA_SEL0);

    Cy_SMIF_Memslot_Init(SMIF_FLASH_HW, (cy_stc_smif_block_config_t * const)&smifBlockConfig, &SMIF_FLASH_context);

   /* Set XIP mode */

    Cy_SMIF_SetMode(SMIF_FLASH_HW, CY_SMIF_MEMORY);

    Cy_SMIF_Enable(SMIF_FLASH_HW, (cy_stc_smif_context_t *)&SMIF_FLASH_context);

They are the same to these codes who are generated by PSOC creator 4.2:

    SMIF_FLASH_Start(&smifBlockConfig, 200);

    SMIF_FLASH_SetMode(CY_SMIF_MEMORY);

smifBlockConfig is generated by SMIF configuration tool: memory mapped, also write enable.

thanks.!

[NiLi_2861801]

PSOC creator, Debug-> memory -> 0x18000000 , data is correct.  but, how to write?

[ShipingW_81 · Accepted solution]

Nick,

Please be aware of that XIP mode does not support functionality such as status reads. This means writing into a flash device not be supported by XIP mode. This is because the writing operation into flash involves not only a write command transfer, but also a status check to verify the status of the operation.

[NiLi_2861801]

Hi fwan,

      Thanks for your reply.  Can SMIF run in CM0 not CM4? I try to move the sample code CE220823 from CM4 to CM0, but it will stop at busy checking ( red line below)

void ReadMemory(SMIF_Type *baseaddr, cy_stc_smif_context_t *smifContext, uint8_t rxBuffer[], uint32_t rxSize, uint8_t *address)

{

    cy_en_smif_status_t smif_status;

    uint8_t rxBuffer_reg;

    cy_stc_smif_mem_device_cfg_t *device = smifMemConfigs[0]->deviceCfg;

    cy_stc_smif_mem_cmd_t *cmdreadStsRegQe = device->readStsRegQeCmd;

    /* Set QE */  

    smif_status = Cy_SMIF_Memslot_QuadEnable(SMIF_1_HW, (cy_stc_smif_mem_config_t*)smifMemConfigs[0], &SMIF_1_context);

    if(smif_status!=CY_SMIF_SUCCESS)

    {

        Cy_SCB_UART_PutString(UART_HW, "\r\n\r\nSMIF Cy_SMIF_Memslot_QuadEnable failed\r\n");

        handle_error();

    }

/* Read data from the external memory configuration register */

smif_status = Cy_SMIF_Memslot_CmdReadSts(baseaddr, smifMemConfigs[0], &rxBuffer_reg, (uint8_t)cmdreadStsRegQe->command , smifContext);

    if(smif_status!=CY_SMIF_SUCCESS)

    {

        Cy_SCB_UART_PutString(UART_HW, "\r\n\r\nSMIF Cy_SMIF_Memslot_CmdReadSts failed\r\n");

        handle_error();

    }

    printf("Received Data: 0x%X\r\n", (unsigned int) rxBuffer_reg);

    printf("\r\nQuad I/O Read (QIOR 0x%0X) \r\n", 0x38);

/* The 4 Page program command */  

    smif_status = Cy_SMIF_Memslot_CmdRead(baseaddr, smifMemConfigs[0], address, rxBuffer, rxSize, &RxCmpltCallback, &SMIF_1_context);

    if(smif_status!=CY_SMIF_SUCCESS)

    {

        Cy_SCB_UART_PutString(UART_HW, "\r\n\r\nSMIF Cy_SMIF_Memslot_CmdRead failed\r\n");

        handle_error();

    }

    while(Cy_SMIF_BusyCheck(baseaddr))

    {

        /* Wait until the SMIF IP operation is completed. */

    }

....

}