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Hi there, I'm currently using Spansion (now Cypress) S29AL016J simulation model (which was downloaded at official site: http://www.cypress.com/simulation-models) in our design. Filename of the model is "s29al016j.v". In our simulation, I found something strange about the model: During CENeg = 1 (viz, chip is NOT selected), some togglings on WENeg and A19~A0 may trigger timing violation, for example: ====== "../../ext_modules/emc_memories/S29al016j/model/s29al016j.v", 1116: Timing violation in tbench.u_emc_flash $hold( negedge WENeg &&& Check:1494554100000, A10:1494554100000, limit: 45000000 ); "../../ext_modules/emc_memories/S29al016j/model/s29al016j.v", 1111: Timing violation in tbench.u_emc_flash $hold( negedge WENeg &&& Check:1494752600000, A5:1494752600000, limit: 45000000 ); ====== In my understanding, when chip is deselected, all other signals including WENeg, Address, are don't care, and toggling on these signals should NOT trigger timing violation. However, my simulation shows otherwise. Can anyone please show me whether I can ignore this timing violation? thx & BR~~
Solved! Go to Solution.
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Hello Xieyl,
Please refer to modeling group response below:
"We should let the customer know that they can ignore the timing violation. We are working on updating the model."
Hope this helps.
Thank you
Regards,
Bushra
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Hello
Thank you for contacting Cypress Community Forum. We will check and get back to you.
Regards,
Bushra
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Hello Xieyuanlu,
I have forwarded your inquiry to our modeling, They are looking into the issue. Please bear with us.
Thank you
Regards,
Bushra
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Thank you buha, expecting your further reply~
BR
xieyl
180329
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Hello Xieyl,
Please refer to modeling group response below:
"We should let the customer know that they can ignore the timing violation. We are working on updating the model."
Hope this helps.
Thank you
Regards,
Bushra
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Hi Bushra,
Thanks for your explanation!
This is a late thank but better late than never 🙂
xieyl
Feb 27, 2020