CE220607 – PSoC 6 MCU Watchdog Timer in Interrupt Mode. Can this example work with CM0p?

[GeIo_1586191]

I'm looking at the CE220607 example and thought to experiment by switching the code across to the CM0p core.

However, when doing so it threw up an error which I was not expecting and did not understand how to fix (if I could fix at all). Hence I decided to ask here.

Error is in this line of code (would normally be found in CM4 main()):

sysint_status = Cy_SysInt_Init(&WDTIsr_cfg, WDTIsr);

It did not like "&WDTIsr_cfg". This is a generated source function found within "cyfitter_sysint_cfg.h" file. The code in this file is as follows:

/* ARM CM4 */

#if (((__CORTEX_M == 4) && (CY_CORE_ID == 0)))

    #define WDTIsr__INTC_ASSIGNED 1u

    extern const cy_stc_sysint_t WDTIsr_cfg;

#endif /* ((__CORTEX_M == 4) && (CY_CORE_ID == 0)) */

So why is WDTIsr_cfg only related to CM4. What is the alternative for CM0p etc.

Thanks

[MeenakshiR_71 · Accepted solution]

Hello GerrikoIoT​,

You will need to enable the interrupt for CM0+ in the Design Wide Resoruces. In the Workspace explorer, under "Design Wide Resources" double-click "Interrupts". In that tab, make sure WDTIsr is enabled (checked) for M0+ (or rather the core you want the interrupt to be mapped to). If you build your project after this, the WDTIsr_cfg will be defined for CM0+.

I guess the above should remove the error.

Regards,

Meenakshi Sundaram R

[GeIo_1586191]

I've just learnt something new today. Awesome! Thanks very much.