using posedge and negedge of clock in same always block

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cross mob
Anonymous
Not applicable

HI

In my Verilog  program using PSOC I want to make an output value (1'b1)for posedge and another output (1'b0) for negedge of same clock .and these two output should come to same output continuously(like 1010101010). is this possible????

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JobinT_31
Employee
Employee
50 solutions authored 25 solutions authored 10 solutions authored

Hi,

It seems the output and the input will be same.

## I want to make an output value (1'b1)for posedge and another output (1'b0) for negedge of same clock .

This can done by using;

always @ (posedge inp_sig)

begin

out1 = 1'b1;

end

But when the first output should go to zero? if it is on negedge of the input signal, you are just generating 3 signals which are same as the input.

Please elaborate the requirement with an example [input/output signal diagram]

Jobin GT

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