Verilog code

[Anonymous]

HI,

I want to give clock pulse in to a output pin,after a count remove that clock.I am attaching my code with this,but this is not working

module component01 (

output reg step,

input   clk,

input   clock

);

parameter count_value = 10;

//reg [count_value:0]count ;

reg [count_value:0] temp_count ;

    always @ (posedge clock)

    begin

        step <= clk;

if(temp_count < count_value)

        temp_count <=  temp_count +1;

    //else

    if(temp_count==count_value)

     step <= 1'b0;

    end

    end

endmodule  

[JobinT_31]

Hello,

Can you please attach the project, so we can try to analyse and debug the issue. I have concerns over the bland line between " if(temp_count==count_value)" and "step <= 1'b0;"

Thanks

Jobin GT