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hello everyone
Iam generating square wave in verilog .I have to give periodcount and dutycycle count values from c code using API calls through 8 bit control register. periodcount and dutycycle count are 28 bit .so iam using four ,8bit control registers. but iam unable to access and concatenate the output of 4 control registers in verilog. Therefore output is not obtained.anyone please give me suggestion to this problem.
I want to be able to read/write it with the software.
Please help!
topdesign
verilog code
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 02/15/2018 at 13:58
// Component: clkgeneration
module clkgeneration (
output reg clkout,
input clk,
input enable
);
//`#start body` -- edit after this line, do not edit this line
reg [31:0] counter; // 12-bit for numbers up to 3999
wire [28:0]control_cr;
wire [31:24]control_crA1;// for periodcount
wire [23:16]control_crB1;
wire [15:8]control_crC1;
wire [7:0]control_crD1;
wire [31:24]control_crA2;// for dutycycle
wire [23:16]control_crB2;
wire [15:8]control_crC2;
wire [7:0]control_crD2;
wire [31:0]period;
wire [31:0]dutycycle;
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregisterA( // name of the control register
.control(control_crA1[31:24])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregisterB( // name of the control register
.control(control_crB1[23:16])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregisterC( // name of the control register
.control(control_crC1[15:8])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregisterD( // name of the control register
.control(control_crD1[7:0])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregister1A( // name of the control register
.control(control_crA2[31:24])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregister1B( // name of the control register
.control(control_crB2[23:16])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregister1C( // name of the control register
.control(control_crC2[15:8])); // output bus [7:0] 'outp'
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
controlregister1D( // name of the control register
.control(control_crD2[7:0])); // output bus [7:0] 'outp'
assign period ={control_crA1,control_crB1,control_crC1,control_crD1};
assign dutycycle = {control_crA2,control_crB2,control_crC2,control_crD2};
always @(posedge clk )
begin
if (enable == 1'b1)
begin
if( counter ==period) // period, count from 0 to n-1
counter <= 0;
else
begin
counter <= counter + 1'b1;
// synchronous output without glitches
if (counter <dutycycle) // duty cycle, m cycles high
clkout = 1'b1;
else
clkout = 1'b0;
end
end
end
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
c code
#include "project.h"
int main(void)
{
CyGlobalIntEnable;
// uint32 periodcount=0x016e3600;
//uint32 dutycycle=0x00b71b00;
/*Place your initialization/startup code here (e.g. MyInst_Start()) */
//uint8 a=periodcount&0xFF;
for(;;)
{
uint32 setperiodcount();
uint32 setdutycycle();
}
}
uint32 setperiodcount()
{
CY_SET_REG8( clkgeneration_controlregisterA__CONTROL_REG,00000001); //
CY_SET_REG8( clkgeneration_controlregisterB__CONTROL_REG,01101110 ); //
CY_SET_REG8( clkgeneration_controlregisterC__CONTROL_REG,00110110 ); //
CY_SET_REG8(clkgeneration_controlregisterD__CONTROL_REG,00000000); //
CR_Write(1);
v=CR_Read();
return 1;
}
uint32 setdutycycle()
{
CY_SET_REG8(clkgeneration_controlregister1A__CONTROL_REG, 00000000 ); //
CY_SET_REG8( clkgeneration_controlregister1B__CONTROL_REG, 10110111); //
CY_SET_REG8( clkgeneration_controlregister1C__CONTROL_REG, 00011011 ); //
CY_SET_REG8( clkgeneration_controlregister1D__CONTROL_REG, 00000000 ); //
return 2;
}
/* [] END OF FILE */
Solved! Go to Solution.
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Please take look at this custom verilog example, which has API to Verilog access
DDS24: 24-bit DDS arbitrary frequency generator component
/odissey1
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Please take look at this custom verilog example, which has API to Verilog access
DDS24: 24-bit DDS arbitrary frequency generator component
/odissey1
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thank you