Anonymous
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Feb 06, 2018
09:55 PM
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Feb 06, 2018
09:55 PM
Hi,
We have used CYW20706UA1KFFB1G and CYW20706UA2KFFB4G variants of 20706 part in our design and we have observed the following behaviour:
When we used “CYW20706UA1KFFB1G” in our design we observed -
- On power-up, when chip is in reset (reset is not released yet, A6-pin is ‘low’) - > BT_UART_TXD (F4-pin) is at logic ‘high’ by default
Now, we have changed to “CYW20706UA2KFFB4G” chip version where we have observed -
- On power-up, when chip is in reset (reset is not released yet, A6-pin is ‘low’) - > BT_UART_TXD (F4-pin) is at logic ‘low’ by default
- After release reset, BT_UART_TXD (F4-pin) is going to logic ‘high’
We request you to help us understand the difference of “BT_UART_TXD” pin default status for above two different versions of chips.
Thank you,
Pravinkumar
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Anonymous
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Feb 07, 2018
10:40 PM
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Feb 07, 2018
10:40 PM
Feb 15, 2018
10:50 AM
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Feb 15, 2018
10:50 AM
Hi Pravinkumar,
Is this change in behavior introducing an issue in your design?
Jacob