PSoC 6 Memory Management

[FrCa_2686456]

Hello!

How do the processors (M0+ and M4) deal with memory management in PSoC 6?

I read that both the M0+ and M4 share access to peripherals and memory. In order to avoid collisions or errors when executing instructions, how does the memory management work?

Please provide links to Reference Manuals or any related info.

Thank you in advance for any help you can provide.

Freddy

[RodolfoGL · Accepted solution]

PSoC 6 has Inter-Processor Management (IPC) block, which can be used for memory management purposes.

You can refer to this code example:

CE216795 - PSoC(R) 6 MCU Dual-Core Basics

You can also refer to the PDL - IPC documentation that comes with PSoC Creator.

[FrCa_2686456]

Yes! This is what I was looking for.

Thank you!