Need S34ML01G2 application note or code examples or library for arm microcontroller

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Anonymous
Not applicable

Hi,

I want to use S34ML01G2 NAND flash in my product. It would be greatly appreciated if I can get an application note or library or code examples related to interfacing with microcontroller(ARM-32bit) inorder to reduce my development time. Please help.

Thanks.

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1 Solution
BacemD_61
Employee
Employee
50 replies posted 50 sign-ins 25 replies posted

Hello,

We don't provide any NAND controller drivers. We only provide NAND chip drivers which are called NAND LLD (Low Level Drivers) and which you can find on our website.

That being said, I would receommend to have a look at the u-boot or Linux samples of the existing controller drivers, e.g: you can find the u-boot NAND related sources for example here:

http://git.denx.de/?p=u-boot.git;a=tree;f=drivers/mtd/nand;h=ab3b4d890dfe7fa8aeb1efba549b85975588fbb...

Many of these controllers are ARM based like:

- "fsl_elbc_nand.c" is the Freescale/NXP NAND controller driver.

- "tegra_nand.c" is the Nvidia Tegra NAND controller driver.

Best regards,

Bacem

---

Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

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11 Replies
BacemD_61
Employee
Employee
50 replies posted 50 sign-ins 25 replies posted

Hello,

We don't provide any NAND controller drivers. We only provide NAND chip drivers which are called NAND LLD (Low Level Drivers) and which you can find on our website.

That being said, I would receommend to have a look at the u-boot or Linux samples of the existing controller drivers, e.g: you can find the u-boot NAND related sources for example here:

http://git.denx.de/?p=u-boot.git;a=tree;f=drivers/mtd/nand;h=ab3b4d890dfe7fa8aeb1efba549b85975588fbb...

Many of these controllers are ARM based like:

- "fsl_elbc_nand.c" is the Freescale/NXP NAND controller driver.

- "tegra_nand.c" is the Nvidia Tegra NAND controller driver.

Best regards,

Bacem

---

Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

Anonymous
Not applicable

We don't provide any NAND controller drivers.

This is sad. Because it seems that Cypress is not being developer friendly(for beginners) who wish to implement NAND flash into their products. Also, I checked Micron's NAND driver and its documentation, they were better documented and developer friendly. Their libraries can be integrated with any microcontrollers.

We only provide NAND chip drivers which are called NAND LLD (Low Level Drivers) and which you can find on our website.

I have already gone through it, but believe me it is very complex and troublesome to integrate it with a microcontroller.

This being said, I think I will have to find my own way out of this if your support for your devices is limited. Orelse I will have to switch over to some other manufacturers who provide better support to their customers.gsns

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Hello,

I'm really sorry about all this!

Our NAND LLD is written in simple Ansi C and should be easy to integrate in any framework. It also has a user guide that details all the functions.

Which controller are you using exactly? I can check its support for our NAND devices in parallel for you.

Best regards,

Bacem

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Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

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Anonymous
Not applicable

Hi Bacem ,

I found this Thread relevant for my issue.

We are facing issues with Multi-plane Erase/write/read  Operation's in my system at U-boot Level. I haven't see any source code with Multi-plane support for your device in generic u-boot mainline code. Hence I started implementing on my Own but no success.

Could you plz help me with Chip LLD with multi-plane Erase/write/read  Operation API's .Which I can integrate in U-boot ?

Best Regards,

-Shravan

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Hello Shravan,

You can download the NAND LLD from here and use it as a reference for your development: Low Level Driver for NAND Flash | Cypress Semiconductor

Best regards,

Bacem

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Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

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Anonymous
Not applicable

Hi Bacem,

On the similar note, i have one question which i hope i can get answer from you or the community here.

My design is pretty old and i am using SMC controller(SMC (PL353)) with ONFI 1.0 support. The NAND device which we are using is: S34ML04G1

The current issue is: all three NAND operations(erase/write/read) are inconsistent.

Thought of using multiplane commands for erase/write/read operations but the doubt is ONFI 1.0 does not have any such support but the NAND device supports this.

Can you please clarify the below:

a. Do you think this combination won't work?

b. why this device is not consistent when i use ONFI 1.0 commands(erase/write/read)?

     Inconsistent symptoms: try writing to a page or block and try to read the data back from same page/block number of times , we see that ~50% chance of getting the right data and the rest is 0xff(data).

Any other suggestions to unblock the issue would really help me.

Best Regards,

Nagi

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Hello Nagi,

Our NAND parts are fully compliant with ONFI 1.0.

Please double check our NAND datasheets for the full set of supported commands and for the right commands to use.

My guess here is that you're not using a proper command, or that you're not waiting enough time for the embedded operation to complete. You will have to check the status register for this.

Try using normal commands without multiplane operation enabling first, to check if the issue is due to multi plane operations or not.

Best regards,

Bacem

---

Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

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Anonymous
Not applicable

Hi Bacem ,

We are usnig SMC(PL353 ) controller with cypress part S34ML04G1.

1. We are able to consistently Read/Write for First page(0) of Every Block(0-2047),as we Read/Write into further pages(1 to 63) facing data inconsistency.  Having no clue what could be the issue plz help.

2. We are using standard u-boot software version(2012) . which by default has the status register check upon every command.

3. In Parallel we having implemented bare-Metal code for ID check, Read /Write and Erase Operation. But , still facing the inconsistency issue.

4. As the chip S34ML04G1 has multi-plane feature. Can we use PAGE-PROGRAM(80h-10h) sequence, Too program with in the plane-0 ?

Inconsistent symptoms: try writing to a page or block and try to read the data back from same page/block number of times , we see that ~50% chance of getting the right data and the rest is 0xff(data)

Request :

Currently we are operating on 50MHz clock , Can you plz provide suitable SMC(PL353) controller timing .This would be highly help full.

These are the current SMC(PL353) Controller timing(50MHz) :

/* Assuming 50MHz clock (20ns cycle time) and 3V operation */

#ifdef SMC_NAND_CLOCK_50MHZ

#define SNAND_SET_CYCLES        ((0x2 << 20) |  /* t_rr from nand_cycles */ \

                                (0x1 << 17)  |  /* t_ar from nand_cycles */ \

                                (0x1 << 14)  |  /* t_clr from nand_cycles */ \

                                (0x1 << 11)  |  /* t_wp from nand_cycles */ \

                                (0x1 << 😎   |  /* t_rea from nand_cycles */ \

                                (0x2 << 4)   |  /* t_wc from nand_cycles */ \

                                (0x2 << 0))     /* t_rc from nand_cycles */

#endif

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Hello,

To solve your issue, I would highly recommend to attach a logic analyzer and capture the bus traffic and then analyze the data. This will help you to find out what's going wrong.

Regarding the timing parameters, I recommend that you relax these timings and test again, e.g: t_rc seems too low.

Here is a working timing parameter table, you can try to get close to these values in your controller registers:

{

.end_of_table             = false,

.manufacturer_code        = 0x01,

.device_code              = 0xd5,

.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,

.chip_size_in_bytes       = 2048LL*SZ_1M,

.block_size_in_pages      = 64,

.page_total_size_in_bytes = 2*SZ_1K + 128,

.ecc_strength_in_bits     = 2,

.ecc_size_in_bytes        = 512,

.data_setup_in_ns         = 20, //tds

.data_hold_in_ns          = 10, //tdh

.address_setup_in_ns      = 25, //tals

.gpmi_sample_delay_in_ns  = 6,

.tREA_in_ns               = 30,

.tRLOH_in_ns              = 0,

.tRHOH_in_ns              = 15,

"S34ML16G200",

}.

Best regards,

Bacem

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Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

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Anonymous
Not applicable

Hi,

As you suggested, i have tried by relaxing the timings(stretched t_rc till 100nSec & t_rea to 50nSec) of SMC-Pl353 Controller for reading. But still facing same issue (inconsistency in Read Page). As the chip is of BGA Package, we are unable to probe Data Lines. Below mentioned are the only signals available to probe on my Eval-Board.

Chip_sel, RE#, WP#, R/B#, WE# Can I perform any understanding activity from these lines?

Thanks,

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Hello,

You would need the IOs as well for the Logic analyzer captures, otherwise you will not have access to the data (address, command, data...).

You can enable DEBUG messages in u-boot and then analyze these messages, maybe this will help you.

For this, you should add the line:

#define debug printf

at the very beginning of the module "nand_base.c".

Please also test with another u-boot version.

This can also be a contact issue on some of the IOs. You can X-RAY the contacts to check this.

Best regards,

Bacem

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Bacem Daassi

Cypress Semiconductor Corp.

Customer Application Engineering

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