How get i rid of setup time violation warnings

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Anonymous
Not applicable

Hello Forum,

i built an DMX-Merger with the PSOC5LP Kit (3 DMX Inputs and 1 DMX Output).

Now i want to setup the clocks as fast as physics allow.

But i get a warning: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( Clock_1 ).

What is the best performance that i can get?

Günter

Static Timing Analysis

Project : Psoc5test
Build Time : 12/28/17 18:54:54
Device : CY8C5888LTI-LP097
Temperature : 0C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0

Expand All | Collapse All | Show All Paths | Hide All Paths

- Timing Violation Section

Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.

ViolationSource ClockDestination ClockSlack(ns)
Setup
CyBUS_CLKClock_1-7.508

- Clock Summary Section

ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
CyILOCyILO1.000 kHz1.000 kHz N/A
CyIMOCyIMO8.000 MHz8.000 MHz N/A
CyMASTER_CLKCyMASTER_CLK80.000 MHz80.000 MHz N/A
CyBUS_CLKCyMASTER_CLK80.000 MHz80.000 MHz49.980 MHzFrequency
Clock_1CyMASTER_CLK4.000 MHz4.000 MHz43.435 MHz
CyPLL_OUTCyPLL_OUT80.000 MHz80.000 MHz N/A
CyXTALCyXTAL8.000 MHz8.000 MHz N/A
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1 Solution
AnkitaS_51
Employee
Employee
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STA warnings , if you open the timing.html of your project you will find the Setup path /violations listed in the project .If you click on them you can see the complete path ,delay contributed by each path and the slack.

if the the slack is negative , you cannot operate the Bus Clk at the set freq, min would be 67 MHz to avoid any STA warnings and issues.

The reason there are STA warnings are because of the Double sync option set in the input pins to the UART component, if you make them transparent, you do not have STA contraints any more.

This is because ,the Synchronization at the pin level is with BUS clock and the delay in UART path cannot meet this timing.

So you can either reduce the BUS clk or change the input UART pins to transparent mode(Double click pin-->Pins-->Input-->Sync mode).

The latter should not have any issues.

If you are concerned about noise ,use good oversampling and 2 out of 3 polling methods.

View solution in original post

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4 Replies
AnkitaS_51
Employee
Employee
100 likes received 50 likes received 25 likes received

http://www.cypress.com/file/179056/download

please see page#14-16 of this AN

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Anonymous
Not applicable

Hello anks,

thanks for your help!

The AN page 14 is about multiple Clocks. I cant see the Problem im my schematics. I use only one clock for all components.

At 48MHz there is no warning.

Günter

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AnkitaS_51
Employee
Employee
100 likes received 50 likes received 25 likes received

STA warnings , if you open the timing.html of your project you will find the Setup path /violations listed in the project .If you click on them you can see the complete path ,delay contributed by each path and the slack.

if the the slack is negative , you cannot operate the Bus Clk at the set freq, min would be 67 MHz to avoid any STA warnings and issues.

The reason there are STA warnings are because of the Double sync option set in the input pins to the UART component, if you make them transparent, you do not have STA contraints any more.

This is because ,the Synchronization at the pin level is with BUS clock and the delay in UART path cannot meet this timing.

So you can either reduce the BUS clk or change the input UART pins to transparent mode(Double click pin-->Pins-->Input-->Sync mode).

The latter should not have any issues.

If you are concerned about noise ,use good oversampling and 2 out of 3 polling methods.

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Anonymous
Not applicable

Thanks anks!

i lowered the oversampling from the UARTs from x16 to x8 and switched the Timer from 16 bit to 8 bit. Then it works up to 77 MHz PLL.

Günter

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