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1. Re: CY14B116N nvSRAM command sequences
boris.yost_3017026 Jan 4, 2018 1:13 PM (in response to boris.yost_3017026)The correct answer is that Note 12 is strictly correct. Table 1 is an example, not a strict enumeration. A15, A[1..0], and of course higher order bits may take any value. There are many possible read addresses for each value of a command sequence.
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2. Re: CY14B116N nvSRAM command sequences
PradiptaB_11 Mar 1, 2018 2:15 AM (in response to boris.yost_3017026)Hi Boris,
As we discussed in the case 00397851 we will be posting our answer on the Forums also.
Regarding your query, for software controlled store and recall operation the address sequence has to followed as given in the datasheet. Now as far as the no of address lines are that are used in software mode they are 13 address lines as mentioned in the datasheet. (A14- A2). Rest all the lines will be dont care for the software mode. In the table the address have been given a specific value to maintain backward compatibility to the older parts.
Say, there is a memory address 0x83E0. In binary it will be 1000 0011 1110 0000. Now only address bits A2 to A14 will be used for the software mode. Bit A15 which is one you can keep it zero also as you want it will not affect the operation. Just for sake of backward compatibility the address is stated as 0x83E0. You can keep it 0x03E0 if you want.
Thanks,
Pradipta.