- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
After receive the CY8CKIT-062-BLE, we test the code sample provided.
We try the code example available into PSoC Creator 4.2 : the dual application (CE213903) works correctly.
We want add a capsense into the APP1, but if we start the Capsense into the cortexM4 main the app1 seems blocked.
however we have an APP1 similar without dual application : in this case, the same code for capsense works.
Could you help us to find the error into the project with dual application?
APP0 : blink a led, check the SW2 state (if SW2 is pressed the PSoC 6 switch into APP1) + uart bootloader
APP1 : just little modification (this APP works perfectly without capsense)
You will find in attachment the project with dual application.
yours
Robin.
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Robin,
please make the following changes in order to fix the issue.
Open bootload_common.ld in App0 and App1 and modify the following values (changes are bolded):
ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x1F00
ram_app0_core1 (rwx) : ORIGIN = 0x08002000, LENGTH = 0x8000
ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x1F00
ram_app1_core1 (rwx) : ORIGIN = 0x08002000, LENGTH = 0x8000
Clean and build both projects. Program App0. Bootload App1.
I've tried using these values and can confirm that it works.
Regards,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Robin,
I've debbuged the issue and it seems that the CapSense ISR is going to the wrong place and the main function is restarted within an interrupt context. (IRQ 49). Afterwards the code hangs on a CapSense busy because the CapSense ISR was not called.
I'll keep looking at this.
Regards,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Robin,
please make the following changes in order to fix the issue.
Open bootload_common.ld in App0 and App1 and modify the following values (changes are bolded):
ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x1F00
ram_app0_core1 (rwx) : ORIGIN = 0x08002000, LENGTH = 0x8000
ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x1F00
ram_app1_core1 (rwx) : ORIGIN = 0x08002000, LENGTH = 0x8000
Clean and build both projects. Program App0. Bootload App1.
I've tried using these values and can confirm that it works.
Regards,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks you cfmm.
I have tried these update : it seems works.
May be i will adjust a the refresh to obtain a better detection for these cap-sense.
regards,
Robin.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The reason for this fix is that the vector table on the CM4 must be 0x400 aligned. Will be fixed in a new release. Thanks for bringing it up.
Yes, I also think 250ms is too long.
Regards,