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Hi,
I'm trying to create a CRC16 (poly 0x1021, initial value 0x0000), and ideally I would like the UDB's to do the serial input XOR (i.e. not using the EXTCRC function).
I'm simulating to confirm the device using the cy_psoc3_dp.v model in the warp sim library and despite having looked at how I should configure and connect the UDB's, I can't get any sensible operation from the simulation.
So firstly I observe that the CRC_v2_40 module in the library uses EXTCRC calculations for the feedback, and I can't find an example that uses the internal feedback, which makes me concerned that there might be an issue with the internal feedback.
Also when I look at the simulation model, cfbo from the least significant byte comes from sir ^ msbo, but I need to feed in the external serial in, into route_si. PSoCCreator will not allow me to feed it into sir (it only expects chaining signals).
I would have expected that in the cfbo equation that sir would be replaced by an s_r_source.
Solved! Go to Solution.
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Attaching a sample project for the requirement.
You can find the modified component in the components tab and see verilog change in crc_v2_40.v file .
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...sorry message got truncated.....
Making this change to the model, gets it running (but still not calculating the correct CRC). But now I'm wondering if I should just be using the EXTCRC mode, or whether there is an issue with the simulation model and/or hardware?
Can anyone shed any light?
Kind regards
Ziggles
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I believe that there is a stock CRC component for UART. Also, UART Rx is typically slow (115kbd) and involves some interrupt processing anyway, so simple software implementation might suffice for CRC check.
odissey1
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