Anonymous
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Nov 30, 2017
11:55 PM
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Nov 30, 2017
11:55 PM
Hi Folks,
I am working with FX3S USB 3.0 controller.
In design FPGA is the master FX3S is slave.
I am using FPGAmaster Verilog code is provided by cypress and I created a block in Vivado .
providing 27MHz input clock to FPGAmaster block and output also 27MHZ clock from FPGAmaster block.
Here, my question will be.
What is expected latency from FPGAmaster block?
Please suggest me regarding this.
Thanks and Best Regards
Vinod Sajjan
1 Reply
Anonymous
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Dec 11, 2017
04:08 AM
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Dec 11, 2017
04:08 AM
Hi,
The various timings are specified in the An65974 application note.
http://www.cypress.com/file/136056/download
Regards,
- Madhu Sudhan