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Hai, I am trying to evaluate the Psoc SPI functionality. I am using CY8CKIT-050 KIT for the same. I am using the SPI_Design Example under the find example project. Working with Psoc creator 3.
The display on the LCD is blank. During debugging, observed the execution halts at.
while(!(SPIS_ReadTxStatus() & SPIS_STS_SPI_DONE));
Help is sought, project folder is attached herewith.
Solved! Go to Solution.
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PSoC 5 Architecture
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PSoC 5LP
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Hai Noriaki Tanaka,
Guess What? after removing the jumpers, The working was as expected. The 1uF Capacitor shunting the SCLK to the ground was acting as a filter attenuating the clock line. Thank you very much. Presuming you are a japanese, 'Doumo arigatou'.
For the benefit of those who might encounter a similar case, let me summarize the 2 hurdles i had to overcome:-
(1) replace while(!(SPIS_ReadTxStatus() & SPIS_STS_SPI_DONE)); with while(!(SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE));
Thank you Bob.
(2) Open Jumpers J43 and J44. Thanks again Noriaki Tanaka.
Henceforth, I shall also scrutinize the schematics of the kit.
Regards,
Samson Richard. B
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You are trying to check transmission (Tx) state of the slave. Better check SPIM__ReadTxStatus() & SPIM_STS_SPI_DONE
Bob
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Hai Bob,
Thanks indeed for the help/suggestion, now the program executes without any halt. However, the data displayed on the LCD are all 0s. The received data by both the master and slave is 0. I have externally looped back all the master and slave lines.
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Did you do the 3rd step described in the Code Example document?
3. Connect the appropriate pins (m_miso to s_miso, m_mosi to s_mosi, m_sclk to s_sclk m_ss to s_ss).
In this code example, the SPI Master (SPIM) controls the SPI Slave (SPIS) and sends/receives data. The SPIS would not receive any data without the 3rd step.
Regards,
Noriaki
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I recognize that you are using PSoC Creator 3.0 SP2. That version of PSoC Creator has no code example document. Can you use a newer version of PSoC Creator? I confirmed PSoC Creator 3.3 has the code example document at following location.
C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\examples\sampleprojects\SPI_Design\SPI_Design.cydsn
Regards,
Noriaki
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Thanks again Noriaki Takana,
I have pulled out the project from find example project, I have illustrated the same in the attachment. However, in the projects under the Kits(CY8CKIT-050 KIT ) there are no examples for SPI. I will anyways install Psoc creator 3.3 or Psoc creator 4 as you suggested and go ahead. Will certainly update the observations and findings thereafter.
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I checked the schematic of CY8CKIT-050 and found the DVK board can have 1.0uF bypass capacitor for the SAR ADC as follows.
Please confirm if the pin headers J43 and J44 are attached and remove jumpers if attached.
These jumpers are connected to m_miso and m_sck respectively and 1.0uF capacitor may affects to the 1MHz clock.
Regards,
Noriaki
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Hai Noriaki Tanaka,
Guess What? after removing the jumpers, The working was as expected. The 1uF Capacitor shunting the SCLK to the ground was acting as a filter attenuating the clock line. Thank you very much. Presuming you are a japanese, 'Doumo arigatou'.
For the benefit of those who might encounter a similar case, let me summarize the 2 hurdles i had to overcome:-
(1) replace while(!(SPIS_ReadTxStatus() & SPIS_STS_SPI_DONE)); with while(!(SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE));
Thank you Bob.
(2) Open Jumpers J43 and J44. Thanks again Noriaki Tanaka.
Henceforth, I shall also scrutinize the schematics of the kit.
Regards,
Samson Richard. B
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Hai Noriaki Tanaka,
Thank you for your reply. I have ensured it. All necessary pins have been looped.