Perhaps some of you clever folks can explain what I'm doing wrong.
As an exercise, I want to use a Datapath (DP) and a state machine (SM) to create a simple serial out like a SPI-lite. My initial implementation was really screwy so I went back to basics to see how the timings work.
What is screwy? My data is shifted out before the DP reaches the instruction to do it.
I have a three-state SM and the state value is used to step the DP so INSTR_ADDR is SM and INSTR_ADDR is SM. So, naturally, as the SM steps unconditionally between the states, the value stored in SM immediately following a clock is that of the forthcoming state and not the one we're in. So if I have a pin where SM == Ready (my states are named Ready, Steady & Go) and another where the pin is set on entering the state and cleared on leaving, the latter is a clock cycle behind the former.
OK. I'm cool with that. If there were an imaginary 2-bit latch, the D-inputs are the value of SM and the Q-outputs are the actual state.
My problem is that my three states control a DP so I expect that the next instruction is set up by the value of SM and actioned at the clock cycle. I have three actions: load the A0 from D0 (loaded with 0x80), shift out the '1', shift out the '0'.
Sorry for being so long-winded.
I expect my data out to change when I enter the 'Steady' state. The SM is set to 1'b1 immediately following entry to the Ready state so when the next clock arrives, I would expect the SM to enter the Steady state and the data appear at the output pin.
It doesn't. It changes as it enters the preceding state. In other words, it behaves as if the clock for the DP were a few nanoseconds behind the change of value of the SM or that the DP were too impatient to wait for the clock and actioned the instruction when the value of SM changed.
Bringing the clock out to a pin, the SM == Ready pin changes 6.6ns behind the clock, the flag set within the state is 3.3ns after the clock and the data changes 4.7ns after the clock. So it can't possibly be a wacky clock.
So, please, why is my data coming out one whole state before it's due?
I'm using a CY8CKIT-050.
Prototype5.cywrk.Archive01.zip 636.0 K