CYW4343W share SDIO interface with eMMC chip

[Anonymous]

Hi,

We are building a product using an MCU which only have one SDIO port that we intent to use to serve both a WiFi interface and a eMMC chip.. We are therefore planing to use an Fairchild FSSD06 SDIO multiplexer. However, we are getting concerned that it might not work as SDIO interrupts using the SDIO_D1 line will be switched off from time to time when the SDIO interface is serving the memory card.

Reading in the documentation it's not clear whether this interrupt capability is mandatory or if the out-of-band interrupt can function in it's place? Also, looking in the various WWD_SDIO implementations, in the WICED SDK, it seems that the STM32F412 implementation doesn't implement this interrupt.

Anyone have any experience with this?

Cheers,

Mogens

[GauravS_31 · Accepted solution]

If you check bus_protocols/SDIO/wwd_bus_protocol.c, the function wwd_bus_write_register_value( BUS_FUNCTION, SDIOD_SEP_INT_CTL, (uint8_t) 1, SEP_INTR_CTL_MASK | SEP_INTR_CTL_EN | SEP_INTR_CTL_POL ) would enable OOB interrupt using separate interrupt control register SDIOD_SEP_INT_CTL. This register would reroute interrupts from SDIO_D1 to an external pad which means that OOB would work in place of SDIO in-band interrupts. You will need to extensively test and ensure that the delay between switching WLAN and eMMC is less than the lowest WLAN SDIO timeout. OOB implementation for STM32F4xx is shown in /WICED/platform/MCU/STM32F4xx/WWD/wwd_SDIO.c.

[Anonymous]

Hi grsr,

Thank you for your response. This is indeed good news. We already see the interrupts on the OOB, but wasn't sure if all interrupts where routed to the OOB pin.

When we started looking to see if this was feasible we made some simple experiments, using a STM32F411 Discovery EVB and a LSR-Sterling extension board. We noticed that the timeout value used in the SDIO driver for the STM32F411 was 50 mSec, which suggested to us that there could be room for sharing the port. We added some simple lock mechanism that locked the SDIO port using a range of lock times with the upper limit of 10-15 mSec, if my memory isn't failing me, to see if it was possible. These experiments did suggest to us that this should be feasible.

We of course need some extensive validation on our platform, but your reply is indeed encouraging.

Cheers,

Mogens