How to read my component's result?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
myz_1382761
Level 1
Level 1

Hello all:

       I created a component use verilog , two frequence inputs ,and generate a 32bits result. like this:

1.png

       the Rst[31:0] no hardware connect, I just need read it to memory, use C API. How can I read verilog result ?  How can I read Rst[31:0] to a long variable ? Or how can I generate C API for verilog to read this result , like long xx_ReadStatus(void){ return Rst; }?

  God , help me!!!

0 Likes
1 Solution
lock attach
Attachments are accessible only for community members.
2. Re: How to read my component's result?

You can use custom component StatusReg32 to read the output of your component (see project attached). Alternatively, you can explore the component files to see how status registers are being implemented and combined in Verilog to make 32-bit register. To use Reg32 component in you project you can either import the component from project attached or set project Dependencies in Project->Dependencies->User Dependencies. For importing components see Cypress tutorial:

http://www.cypress.com/video-library/PSoC-Software/psoc-creator-tutorial-importing-components/107756

Use the StatusReg32 same way as Cypress stock StatusReg component. See demo attached.

Reg32_01b.png

View solution in original post

0 Likes
10 Replies
NoriTan
Employee
Employee
25 sign-ins 5 questions asked 10 sign-ins

Followings are my solution for your component.

GS003265.png

The first solution is using your component and the Status Register component.  The "Status Register" component gets a 8-bit value generated by hardware from a software.  Because the maximum bit width of Status Register is 8-bit, please be careful about the consistency between multiple Status Registers.

Second solution is to implement a component with UDB's Datapath.  The datapath has FIFO to read a 32-bit value at once and the CPU can read the FIFO via registers on the address map.

GS003266.png

Third solution is to use the Counter component provided by Cypress.  When you implement a 32-bit counter using a Verilog's register, the macrocells in the PLD part of the UDB are used.  This takes more resource and more timing slack.  If you can use the Counter component, the component is generated using the Datapath with few resource and the maximum frequency is higher than one using Verilog register.

Regards,

Noriaki

0 Likes
lock attach
Attachments are accessible only for community members.
2. Re: How to read my component's result?

You can use custom component StatusReg32 to read the output of your component (see project attached). Alternatively, you can explore the component files to see how status registers are being implemented and combined in Verilog to make 32-bit register. To use Reg32 component in you project you can either import the component from project attached or set project Dependencies in Project->Dependencies->User Dependencies. For importing components see Cypress tutorial:

http://www.cypress.com/video-library/PSoC-Software/psoc-creator-tutorial-importing-components/107756

Use the StatusReg32 same way as Cypress stock StatusReg component. See demo attached.

Reg32_01b.png

0 Likes

Thank you very much . But I have a doubt for the read function:

            return  ((uint32) CY_GET_REG8(`$INSTANCE_NAME`_sts0_PTR))     |

                    ((uint32) CY_GET_REG8(`$INSTANCE_NAME`_sts1_PTR)<<8u) |

                    ((uint32) CY_GET_REG8(`$INSTANCE_NAME`_sts2_PTR)<<16u)|

                    ((uint32) CY_GET_REG8(`$INSTANCE_NAME`_sts3_PTR)<<24u); // combine into 4-byte word

Every time read 8 bits part , is this no byte consistency problem? For example , 32bit result is first 0x11223344 , and change to 0x22334455 after I read two bytes , the final I read is 0x22333344.

0 Likes

I believe that Reg32 components work correctly, but more tests would be better. You may test it using project provided. If test shows that it is OK, then the issue in verilog implementation.

0 Likes

Thank you

0 Likes

Thank you very much , I'm trying the second

0 Likes

Hi , can you give me a demo about read datapath 32bits FIFO?

0 Likes

I have no such demo readily available. Use CY_GET_REG32(...).

0 Likes

There is a hit in the Timer/Counter component's API functions.

In the Counter component's C source code file, there is an API function Counter_ReadCounter()  The API function is described as follows.

uint32 Counter_ReadCounter(void)

{

    /* Force capture by reading Accumulator */

    /* Must first do a software capture to be able to read the counter */

    /* It is up to the user code to make sure there isn't already captured data in the FIFO */

    (void)CY_GET_REG8(Counter_COUNTER_LSB_PTR_8BIT);

   

    /* Read the data from the FIFO (or capture register for Fixed Function)*/

    return (CY_GET_REG32(Counter_STATICCOUNT_LSB_PTR));

}

At first this API reads the accumulator in 8-bit and then reads the FIFO register in 32-bit.

This operation is named as "FIFO Software Capture Mode" and described in the "PSoC 5LP Architecture TRM, Document No. 001-78426" as follows.

GS003275.png

I'm sorry but I don't enough time to prepare a sample project right now.

Regards,

Noriaki

0 Likes

Think you very much

0 Likes