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AN69574 examples work well when PCLK is 100MHz.
If PCLK less than 80Mhz Control center show error 997
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What is the host controller?
Are you trying Stream_IN or Stream_OUT or LoopBack?
Can you try the same with GPIFtoUsb Example project: \EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxgpiftousb
You can change to PCLK by varying the first argument to 5 from 4 in the following Variable and build the project then try
CyU3PPibClock_t pibClk = {4, CyFalse, CyFalse, CY_U3P_SYS_CLK}; This changes the PCLK to 80 MHz.
Note that this example does not need any external processor.
I attached the image file with CyU3PPibClock_t pibClk = {5, CyFalse, CyFalse, CY_U3P_SYS_CLK};
Load this and do IN Transfers in the control center the update.
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May be the Timing of FPGA is not match with clk_80M?
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Hi Wu,
The timing issue on the FPGA side could be a problem. If you suspect so, please investigate in that point of view.
Regards,
-Madhu Sudhan
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hi madhu sudhan I am working with GPIFtoUSB fx3 firmware example ,after I build the firmware when I try to boot by control center its not enumerating the elf, so endpoints are not detecting.