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Here is our desired configuration on a BCM20736SIP:
1. boot from internal I2C EEPROM
2. leverage the NVRAM functionality of the internal I2C EEPROM
3. use SPI1 as a master
4. use SPI2 as a slave
Is this possible to do all this at the same time? There are quite some threads stating that on a SoC this doesn't work. But we are not sure if the SIP has similar restrictions. especially since SCL and SDA share the CLK and MOSI on pins 15 and 16.
Solved! Go to Solution.
- Labels:
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FlashEEPROM
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I2C
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SDK 2.X
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SPI
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Your understanding is correct. On the SIP, the SCL+SDA pins are shared with SPIFFY1 (SPI 1), so SPI 1 is not available.
Items 1,2 and 4 from your list should work with no problems as many customers use these three items together in their design.
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Your understanding is correct. On the SIP, the SCL+SDA pins are shared with SPIFFY1 (SPI 1), so SPI 1 is not available.
Items 1,2 and 4 from your list should work with no problems as many customers use these three items together in their design.
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So another question:
would it be possible to use SPI1 for boot and then use both SPI1 and SPI2 •without• I2C?
Or use I2C for boot and then activate SPI1 and ignore I2C up until the next reboot?
We really need two independent SPI interfaces, one as master and one as slave and looking for a way to do this.
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I know at one time the developers were trying to devise a way to switch between SPIFFY1 (Fast Boot) and I2C (Sensor input), but I'm not sure if anything ever matured from this idea. It seems technically possible to use both functions.