Hi Colin,
From the TRM,
4.1.3 Interrupts
Interrupts, in a multi-page SRAM PSoC device, operate the
same as interrupts in a 256 byte PSoC device. However,
because the CPU_F register is automatically set to 0x00 on
an interrupt and because of the non-linear nature of interrupts
in a system, other parts of the PSoC memory paging
architecture can be affected.
Interrupts are an abrupt change in program flow. If no special
action is taken on interrupts by the PSoC device, the
interrupt service routine (ISR) could be thrown into any
SRAM page. To prevent this problem, the special addressing
modes for all memory accesses, except for stack and
MVI, are disabled when an ISR is entered. The special
addressing modes are disabled when the CPU_F register is
cleared. At the end of the ISR, the previous SRAM addressing
mode is restored when the CPU_F register value is
restored by the RETI instruction.
Therefore, all interrupt service routine code will start execution
in SRAM Page 0. If it is necessary for the ISR to change
to another SRAM page, it can be accomplished by changing
the values of the CPU_F[7:6] bits to enable the special
SRAM addressing modes. However, any change made to
the CUR_PP, IDX_PP, or STK_PP registers will persist after
the ISR returns. Therefore, the ISR should save the current
value of any paging register it modifies and restore its value
before the ISR returns.
So as long as you preserve and restore those _PP register, you are ok.
Also, during an interrupt the GIE is disabled, so that no other interrupt can occur during an ISR, unless you enable GIE in the ISR.
From the TRM
GIE is also cleared automatically when
an interrupt is processed, after the flag byte has been stored
on the stack, preventing nested interrupts. If desired, the bit
can be set in an interrupt service routine (ISR).
