How to set cy7c68013a endpoint2 work as quad buffers with 1024Bytes?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Anonymous
Not applicable

 I tried so many times to set cy7c68013a endpoint2 work as quad buffers with 1024Bytes to accomplish higher speed , but failed,my initial codes are as follow, the handbook just note to set bit SIZE in regester EP2CFG, is there something important be ingnored? Could somebody help me ?

   

 

   

   

void TD_Init( void )

   

{ // Called once at startup

   

    CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

   

    //  FIFOPINPOLAR |= 0x03;

   

    SYNCDELAY;

   

    PINFLAGSAB = 0x08; // FLAGA - EP2EF

   

    SYNCDELAY;

   

//    PINFLAGSCD = 0xE0; // FLAGD - EP6FF ??flag??

   

//    SYNCDELAY;

   

    PORTACFG |= 0x80;

   

    SYNCDELAY;

   

    IFCONFIG = 0xE3; //1110 0011 for syncslave fifo

   

    SYNCDELAY;

   

  EP2CFG = 0xa8;        //1010  1000       //out 1024bytes, 4x, bulk 4<<<<<<<<<<<------

   

  SYNCDELAY;                    

   

  EP6CFG &= 0x7f;                // in 512 bytes, 4x, bulk 4???

   

  SYNCDELAY;              

   

  EP4CFG &= 0x7f;                //clear valid bit

   

  SYNCDELAY;                     

   

  EP8CFG &= 0x7f;                //clear valid bit

   

  SYNCDELAY;

   

  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

   

  SYNCDELAY;                    // see TRM section 15.14

   

  FIFORESET = 0x82;             // reset, FIFO 2

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x84;             // reset, FIFO 4

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x86;             // reset, FIFO 6

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x88;             // reset, FIFO 8

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x00;             // deactivate NAK-ALL

   

  // handle the case where we were already in AUTO mode...

   

  // ...for example: back to back firmware downloads...

   

  SYNCDELAY;                    // 

   

  EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1

   

  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

   

  SYNCDELAY;                    // 

   

  EP2FIFOCFG = 0x11;            // AUTOOUT=1, WORDWIDE=1

   

  SYNCDELAY;                    // 

   

  // enable dual autopointer feature

   

  AUTOPTRSETUP |= 0x01;

   

}

0 Likes
1 Solution
Anonymous
Not applicable

 Hi ,

   

Set the values of EP2CFG=0xAC;

   

EP2CFG.2 bit is used to set the size of the buffer. If it is zero, the size of the buffer is 512Bytes and if it is '1', size of buffer is 1024Bytes. For more details refer page number 235 in TRM (http://www.cypress.com/?docID=45142) .

   

 

   

Regards,

   

Vikas.

View solution in original post

0 Likes
8 Replies
Anonymous
Not applicable

 Hi ,

   

Set the values of EP2CFG=0xAC;

   

EP2CFG.2 bit is used to set the size of the buffer. If it is zero, the size of the buffer is 512Bytes and if it is '1', size of buffer is 1024Bytes. For more details refer page number 235 in TRM (http://www.cypress.com/?docID=45142) .

   

 

   

Regards,

   

Vikas.

0 Likes
Anonymous
Not applicable

Hi,Mr.RSKV

   

I tried to set EP2CFG = 0xac; and still can't set it work as quad buffers with 1024Bytes,actually EP2CFG .3 is the SIZE bit, I wonder whether there are another register should be set or the assembly file DSCR.A51 should be changed.

   

I want to set it work at that mode because in my project,I can only achieve 10M bytes/s(test as the chip work as quad buffers with 512B and bulk transfer,client software in PC send 32K bytes per package,the client software write base on cyapi)

   

Thanks very much,

0 Likes
Anonymous
Not applicable

 Dear MR. VAVC ,Can you help me solve the problem, thank you very much

0 Likes
Anonymous
Not applicable

 Hi ,

   

I am sorry, size bit is EP2CFG.3 not EP2CFG.2. 

   

Even if you configure the  end point buffer size as 1024 (with quad buffer), you cannot  use the total 4K buffer size.

   

For more information please refer the link  http://www.cypress.com/?id=4&rID=31675

   

 

   

Regards,

   

Vikas.

0 Likes
Anonymous
Not applicable

That's a very useful information, and means I must find another way to achieve higher speed. Do you know whether the chip can achieve 35M bytes/s in bulk transfer mode or mush in Isochronous mode?

   

Thank you very much.

0 Likes
Anonymous
Not applicable

 Hi,

   

Please see http://www.cypress.com/?docID=46107

   

Regards,

Anonymous
Not applicable

 Thanks,  I will read it careful and have a try.  

   

I't seems that the pdf file mainly talking about ISO transfer,but the  firmware is about BULK transfer. I have tried ISO transfer but found it much slower than BULK transfer. I only modified the register EP2CFG so some parameter may be ignored, 

0 Likes
Anonymous
Not applicable

 Hi, I tried the example project an4053, I download the .iic file but the original driver can't  be used, so I copied the initial coeds for ISO transfer to my project and changed dscr.a51 file , I only acquire about 5MB/s and much slower than bulk transfer (15MB/s). Does somebody know how to use and debug the project AN4053? Thanks a lot.

0 Likes