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Hi there,
I need to implement a I2S transceiver to perform some audio transform in PSoC, and add this PSoC into an existing I2S audio path. Obviously, I need a I2S receiver working in slave mode to receive audio and a I2S transmitter working in master mode to send out audio. I have problem here since there is no component capable of receive I2S in slave mode. So I ended up post my question here:
Is it possible to receive I2S in slave mode with PSoC?
Best Regards,
CY
Solved! Go to Solution.
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PSoC 1
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The only ready solution I can see so far is for PSoC3/5 a I2S-master.
When you are REALLY in need of a I2C-slave you will have to implement it yourself using a PSoC3/5 (preferrably PSoC5), some of the internally availlable UDBs containing DataPaths and programming them in HDL using VeriLog.
Not an easy project but it can be solved.
So far I cannot see an easy solution for PSoC1
Bob
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The only ready solution I can see so far is for PSoC3/5 a I2S-master.
When you are REALLY in need of a I2C-slave you will have to implement it yourself using a PSoC3/5 (preferrably PSoC5), some of the internally availlable UDBs containing DataPaths and programming them in HDL using VeriLog.
Not an easy project but it can be solved.
So far I cannot see an easy solution for PSoC1
Bob
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PSOC 4 also has I2S -
http://www.cypress.com/psoc4/?source=CY-ENG-HOMEPAGE&medium=Body-Products
Regards, Dana.
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On I2S specfication from Philips. There are sugested crcuit for reference.
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Hi Bob,
Thanks to your informative response about the UDB feature availibility among different PSoC series. Now I know that PSoC1 is probability not what I am looking for. It is also good to know that UDB allow custom logic design.
Best Regards,
CY
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It could be tempting to use a PSoC4 which comes on a VERY cheap (&4) prototyping board but it has got only 2 UDBs which might be too tough.
Bob
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Even though PSOC 4 has only 4 UDBs it has additional fixed function
HW like 2 SCB blocks and 4 16 bit timer/counter blocks, which UDBs
often consimed by. So for a $ 1 - $ 2 part, with ARM core, not too shabby.
Regards, Dana.
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All,
I too am interested in having an I2S Slave transciever. In my case I need both Rx and Tx in slave mode. I'm working on a project that involves taking L/R I2S data off a surround sound receiver, processing it, then re-inserting the data back into the receiver. I've sucessfully gotten the system to work on an Altera FPGA, but I used their built in mega-function FIR filter and I had to write my own I2S decoder and encoder in VHDL.
I'd like to port this project over to using the UDB and DFBs to implement the filtering on a PSOC5 chip. (I wish I had known about the PSOC5 planned obsolescence, I would've purchased the PSOC5LP).
I've never used the built in filters on a PSOC design. I wonder if it can handle the math of my four 256-tap FIR filters, but I'd like to give it a try.
Question:
Why didn't they just build the I2S with Master and Slave options? It really couldn't have been that much more work.
Possible Solutions:
1- I could write some kind of FIFO that took the data in with the off chip master control signals and then allow data to come out based on the timing of the PSOC control signals (eg. sck, ws), but then I'd have to figure out how to syncronize the ws signals together so that the output data of the FIFO is frame or word aligned with the input to the PSOC I2S.
2- I could port my VHDL code to Verilog then import the decoder and encoders into the UDB blocks. This would probably be the easiest, asside from Cypress redesigning the I2S Component and making it backward compatible with the PSOC5 chips. (not likely to happen)
Any Suggestions?
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Cypress will replace your PSoC5 (Kits and chips) with PSoC5 LP for only the shipping fee. So you will be able to use PSoC5 with the latest Creator versions.
Bob
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One way to input I2S data in slave mode is to use an external asynchronous sample data converter (ASRC) chip like CS8421:
http://www.cirrus.com/en/products/cs8421.html
You just config both the input and the output ports as slave by connecting 1k resistor from MSEL pin to GND.
Obviously that solution is not "bit perfect".
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I've never used the built in filters on a PSOC design. I wonder if it can handle the math of my four 256-tap FIR filters, but I'd like to give it a try.
What is the sampling rate you are targeting for each filter ? The PSOC 3/5/5LP has a DigitalFilter block,
current GUI capability is 2 channel, 128 taps total for its 2 channel architecture. Note each channel
can be a cascade of 4 individual stages, for example a cascade of 4 biquad stages. GUI supports
both IIR and FIR. PSOC 4 does not have a DFB, but does have a 32 x 32 single cycle multiplier, 32 bit
result.
The DFB is a general purpose block when used with the DFB assembler, so if the GUI is too limiting
you can roll your own. Coupled with DMA very capable architecture.
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Hi
I have made one, and it took me two weeks. It is rough when you know nothing of UDBS, luckily I have imported the I2S master component and used it to find out how to do.
I made it for my open source audio amplifier, a project called Modac. It can be found here: Patrick Areny / Modac · GitLab
Please keep the copyright notice on this file, and share if you have something new.
Patrick