Connecting FX3 with 2 ADC

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Anonymous
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Hi! How to configure GPIF port so that the rising edge of CLK (from external clock, 25 MHz) at 32 bits from port stored in a buffer? Once the buffer is filled, it is sent to the PC.

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Anonymous
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        Hi, Please have a look at the attached example project. That project is developed for reading data from ADC. Thanks, sai krishna.   

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18 Replies
Anonymous
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        Hi, Please have a look at the attached example project. That project is developed for reading data from ADC. Thanks, sai krishna.   
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Anonymous
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        Unfortunately, I can`t find the attached project   
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Anonymous
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Hi,

   

Sorry for that and attaching again.

   

Thanks,

   

sai krishna.

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Anonymous
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        Hi, Thanks for your help! I select synchronous slave 32-bit interface with external positive clocking. I have a problem with state machine. In example is not clear for which there are two streams and how they interact with ports. I tried to make state machine to my device. After power up THREAD0 read data from GPIF-porr into buffer. After filling buffer generates DMA_RDY_TH0, right? How to transfer data from the buffer to USB-port?   
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Anonymous
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Hi,

   

Let say you have allocated buffer of 16KB size and count as 4 to the DMA channel that you are creating between PIB socket and USB socket. If you are using single thread then it will allocate 4*16KB buffer. But if you are using two threads and DMA many to one channel then it will allocate 4*16KB buffer for each thread.

   

Let say GPIF II already read 16KB of data from the ADC and then GPIF II is reading the next byte (16KB plus...)

   

Then DMA channel switches to the next 16KB buffer. But this switching includes some definite amount of delay.

   

So to avoid this we are using two threads in the attached example. This thread switching does not include any delay.

   

So as soon as the buffer allocated to TH0 is filled then we start filling buffer allocated to TH1.

   

In the mean time, buffer switching happens for TH0 and TH0 will be ready to accept new data bytes. As soon as first buffer allocated to TH1 is filled it will switch to second buffer allocated to TH0 and this process goes on...

   

I hope this explanation help you with your design.

   

Please let me know if you have any more questions.

   

 

   

Thanks,

   

sai krishna.

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Anonymous
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Hi! With streams was clear, thanks! Now  I made the project with a single thread (files attached). Unfortunately, the board sends the wrong values​​ and after some packets return error 997 (see attached image). I think I still incorrectly configured DMA and draw state machine.

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Anonymous
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Hi,

   

Please try with the attached GPIF II project.

   

I just changed the state transition from Logic_One to DMA_rdy_TH0. We should be checking for readiness of the buffer we perform IN_DATA action. We can know this with the help of DMA_RDY_TH0 flag.

   

Please let me know the behavior of your project with this project.

   

 

   

Thanks,

   

Sai Krishna.

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Anonymous
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Hi! Tomorrow I will try to use the previous example in my project. Please attach the modified project again).

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Anonymous
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        PFA, Thanks, sai krishna.   
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Anonymous
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Yahooo! Working!!! big thanks!!

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Anonymous
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Example with 2 threads does not work correctly. Max paket size = 16384. After I read 2 packets from device (data is correct) next read action return error 997. If I set LD_DATA_COUNT to 32766 (in GPIF II designer), error raising after 12 read actions. If I set CY_FX_DMA_BUF_COUNT to 4 - error after 8 read action. Buffer overflow? Why?

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Anonymous
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        I can`t understand why such behavior. Please help me!!   
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Anonymous
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 Hi there,

   

 

   

We are also pursuing the same configuration (ADCs streaming data into FX3) and are very interested in a resolution to the problem Sinc is experiencing.

   

 

   

Additionally when we load the attached projects the simulation waveforms are present in the version supplied by Sinc, but in the version supplied by RSKV we are unable to see the data trace and GPIF II designer reports "Invalid state machine path for the simulation for state RD_DATA"

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Anonymous
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Hi Sinc and Aiden,

   

Please try with the attached project.

   

Thanks,

   

sai krishna.

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Anonymous
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Anonymous
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        Hi! Try attached solution. Solution work on PC (chipset X79, win 7), but does`t work on 2 ultrabooks (chipset hm76, win 8). Maybe, problem with driver. Good luck!   
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Anonymous
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Hi, RSKV. Your last example the best! )) Thank you!

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Anonymous
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Good to hear that Sinc

   

Regards,

   

sai krishna.

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