How to make DDS module

[Anonymous]

Hello PSoCers     

   

I am willing to submit this article.     

   

Still getting started this component division.     

   

i am afraid of some rudeness of mine.     

   

don't know the rule of this division yet.     

       

In my practice, DDS module become working.     

   

There are many items to have improvements.     

   

I want to listen to how to get more efficiency.     

   

Want to listen to critique from everyone     

       

I have been work with Xilinx CPLDs,     

   

those works are mainly schematic-base design.     

   

I am new to PSOC CPLD and Warp-Verilog.     

       

Keep it up rolling !     

[Anonymous]

        Thank you fellows   
As see it, Actually this field is not adaptive to use PSoC   
There are many dedicated ASIC chips, doing genious work.   
Nonetheless, Oscillation is basic circuitry of all device.   

[Anonymous]

Hi PSoC73

       

Many thanks your new examples this produce nice sounds 🙂

       

Kamil

[Anonymous]

My next experience implements Dana´s IIR filter sine with simple verilog wolfram pattern generator.

       

Kamil