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Hi,
I rencently began some tests on 2 CY3275 devkits communicating together (low voltage 12/24V PLC devkits).
I displayed the output signal (FSK) on an oscilloscope and figured out that the packet isn't transmitted within the expected time.
I modified the example programs in order to send a full 39B packet (1B (0xAB) + 6B header + 31B data + 1B CRC). So it should take approximately 130ms @ 2400bps to be transmitted.
The oscilloscope shows me that the packet takes 200ms to be transmitted.
Solved! Go to Solution.
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Take my comments with a grain of salt as I have never used the
kit before, but in the protocol firmware is there a variable keeping track
of packet retrys due to power line noise ? That may be an indicator
of performance.
You could always put a scope on infinte persistance and look at the
power line to get a handle on pk-pk noise over time.
Regards, Dana.
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Take my comments with a grain of salt as I have never used the
kit before, but in the protocol firmware is there a variable keeping track
of packet retrys due to power line noise ? That may be an indicator
of performance.
You could always put a scope on infinte persistance and look at the
power line to get a handle on pk-pk noise over time.
Regards, Dana.
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I always calculate a serial transmition with 12 bits / byte since there are start- and stop-bits and a parity as well. When I take your 38 bytes @2400 baud I get 195ms which is rather close to your observed 200ms.
Bob
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Bob, I must be missing something.
8 bits/byte + 1 stop + 1 start + 1 parity = 11 bits x 38 bytes x 1 / 2400 baud = 174 mS
Regards, Dana.
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Ah, I missed 2 stop bits vs 1.
Senility is closing in rapidly.
Regards, Dana.
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It is not named senility, it is named dyscalculia and it may be healed by having 27 pirimes and a qube a day.
Bob
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Thank you for your replies !
I didn't know there was start/stop/parity bits for each byte transmitted. Can it configured or bypassed ?
Thank you
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Startbits are essential and cannot be avoided (maybe changed in length), stopbit can be ommitted (usually). Parity may be ommitted, but since the protocol is standardized you should stick to the default. Check datasheet of usermodule and PSoC.
Bob
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Odd, I cannot seem to find a EIA spec on serial UART, 16550 basis,
but doesn't the receiver need at least 1 stop bit to avoid a framing error ?
www.freebsd.org/doc/en/articles/serial-uart/
en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter
Regards, Dana.