Using multiple 74HC595 shift register on PSoC 3 with LATCH function

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Anonymous
Not applicable

 Hi everyone,

   

the project I'm working on contains 21 outputs multiplexed on 3 shift registers 74HC595 cascaded. I'm controlling them with a DATA pin, LATCH pin and a clock. I need to refresh these 21 outputs very fast (at 25kHz) and I don't want the CPU to be overload by it because it's already managing many tasks. I think I can use a ShiftReg component to automate the process of refreshing outputs, but I don't know how to put down the LATCH pin during the shifting time in the 74HC595. And if possible, I would like to keep it automatised in order to not occupied the CPU.
Does anyone know how I could do? or maybe did that in a project?

   

Thank you,

   

Nicolas

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HeLi_263931
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You can use a SPI component to drive a '595 register. And the SPI master can drive the slave select signal automatically - you just need to route it to the appropriate register before starting to send a byte.

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ETRO_SSN583
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You could consider a 24 bit Creator SR componenty + a LUT to develop 595 control, select,

   

clocking signals.

   

 

   

Or

   

1) Datapath tool

   

2) Simple verilog solution.

   

3) Even the  DFB assembler

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Yes but a LUT contains only 32 states maximum and I think I need two state by bit to shift no? one clock edge to put the bit on the output of the PSoC, and one clock edge to shift it on the 74hc595 ; so with these suppositions I don't have enough states on a LUT.
Maybe, can you be more specific with your solutions?

   

Thank you for your care and your answering speed 🙂

   

Nicolas

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Bob_Marlowe
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Within a PSoC 3/5 are 24 8-bit wide chainable UDBs each containing 2 FIFOs (4 stages deep) an ALU (programmable) that can shift, some registers and other usable logic all running without CPU intervention.

   

The only difficulty might be that you have to use an HDL-language named VeriLog to describe what the UDB shall perform.

   

Have a look here www.cypress.com/ 

   

 

   

Bob

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ETRO_SSN583
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I was not thinking of LUT to handle entire solution, for your stated reason.

   

What I think is start with 24 bit SR,  use LUT or a counter (3 bits) to count off 8 bits

   

while shifting, on 9th bit (counter overflow) advance enable to next 595. I have not

   

looked at 595 but first thought is to tie 24 bit and 595 clocks (and data out 24 bit SR

   

to all 595 data ins) to same source, then just switch enables every 8 bits in a round

   

robin fashion. Setup/Hold and enable functionality have to be examined.

   

 

   

Or LUT driven by 8 count (3 bits) counter overflow to develop 3 enables. Again used

   

in conjunction with 24 bit SR.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 I’m not using the Enable pin on the 595, you can see the electrical configuration on the last diagram off this page : http://arduino.cc/en/tutorial/ShiftOut#.UxTFIPl5N5I

   

So I have to manage the send of the 24 bits in one time     

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ETRO_SSN583
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Thats even easier than I thought.

   

 

   

So the 595's are all connected in series, SO to SI from one part to another.

   

 

   

Then just use the SR module on PSOC, config it as 24 bits, tie SO of

   

24 bit SR to SI of first in chain 595.

   

 

   

No all we have to do is from some starting point, write the data to 24 bit SR, then

   

supply 24 clocks and stop.  Something like below. Note you might wnat top invert

   

colcks to 595's so they have plenty of setup/hold, eg. clock on opposite edge as

   

24 bit SR and 24 count counter.

   

 

   

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ETRO_SSN583
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Correction to schematic, we do not need to reset the SR, the write to it takes

   

care of that.

   

 

   

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Bob_Marlowe
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Now I am curious how you manage to get the 24 parallel output lines...

   

 

   

Bob

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ETRO_SSN583
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He is not trying to replace the 3 - 74HC595's, just load them.

   

 

   

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ETRO_SSN583
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By the way, if you want a SIPO part with a lot of drive capability for

   

high power LEDs, take a look at -

   

 

   

www.ti.com/general/docs/lit/getliterature.tsp

   

 

   

595's are pathetic, think dribbling currents.

   

 

   

Regards, Dana.

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ETRO_SSN583
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I made one more change, did not like fact clock did not start and end

   

low. Also eliminated SIN on the 24 bit SR.

   

 

   

int main( void ) {

    CyGlobalIntEnable;
   
    ShiftReg24_Start( );
    Cnt24clks_Start( );
    for(;;)
    {
        /* Place your application code here. */
       
        ShiftReg24_WriteRegValue( 0x876543 );
        Burst24Bits_Write( 1 );                                // Clear D, start clock again
        Burst24Bits_Write( 0 );
        CyDelay( 1 );
       
    }
}

   

 

   

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Anonymous
Not applicable

 Thank Dana, it seems to be simpler way! and if i'm correct I can place the Latch pin of 595's on the node just after the not gate of the D flip flop?

   

I'll try this as soon as I receive my the printed circuit.

   

By the way it's not to control leds but thanks again, the component you propose could be usefull for other applications.

   

Nicolas

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Anonymous
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We used to have an issue with shift register of PSoC3, it seems to need one extra clock on the very first time that it was used power up, It worked correctly afterwards. Were in a hurry that time we just performed a dummy shift operation first.

   

It was with creator 2, not sure if that is still the case for creator 3 with the updated library. 

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Bob_Marlowe
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@Dana,

   

...and I thought the LEDs should be connected to the registered outputs, thus my post to use UDBs.

   

 

   

Bob

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ETRO_SSN583
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Regarding the latch signal, from datasheet -

   

 

   

Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.

   

 

   

So I think it should be -

   

 

   

   

 

   

 

   


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Bob_Marlowe
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Untested, but should work.

   

 

   

Bob

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ETRO_SSN583
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Bob, my design has issues which I am working on. Runt pulse

   

problem.

   

 

   

The one you posted. I think his 74HC595's are on another

   

PCB, eg. he is trying to interface to them, not reproduce them ?

   

In any event you have not latched them like a 595 does. So all

   

outputs update to new value once and only once, not 24 times

   

as they are being shifted into position.

   

 

   

Regards, Dana.

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Bob_Marlowe
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Oh, I thought that everything should be stuffed into the PSoC

   

By the way: It is rather easy to provide an 8-bit latch for each of the shift-registers on schematic or in VeriLog.

   

 

   

Bob

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ETRO_SSN583
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Yes, no end to what we could add with Verilog.

   

 

   

Regards, Dana.

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ETRO_SSN583
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Elganor, here is latest version of clking system for the HC shift registers.

   

I am still not happy with clocks as I get runts at last clk. Although it is

   

1/2 period wide, more than enough to satisfy external SR clcocking, its

   

not a "clean" design as far as I am concerned. But at least a starting point.

   

 

   

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MiSi_284936
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 I'm running out of pins on the PSoc3 and was considering similar.

   

But the 595 can be done as simple as:

   

http://mbed.org/users/hexley/notebook/a-simple-spi-port-expander/

   

then just use a SPI for it.

   

Currently two 74hct595's cost more than a Microchip MCP23S17 which can be adjusted for input or output, and less room.

   

Coding of course simpler for 595.

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ETRO_SSN583
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Excellent idea, but his design needs 24 bits worth of 595's to feed. Actually

   

shows how great it would be if SPI was not limited to 16 clks/bits.

   

 

   

Ideally we would use a 24 bit widget to hold the data (24 bit SR ?) and simply

   

write the value into SR and then generate 24 clks to the SR and stop, get ready

   

for next 595 update.

   

 

   

Regards, Dana.

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ETRO_SSN583
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This seems to be working with no runts, etc.., although not tested with

   

actual 595's

   

 

   

    Burstctrl_1_Write( 1 );                                        // Force bit cntr and clks to SR to stop
    ShiftReg24_1_Start( );                                        // Startup the SR
    Cnt24clks_1_Start( );                                        // Starup the counter
    Burstctrl_1_Write( 0 );                                        // Force bit cntr and clks to SR to start

    for(;;)
    {
        /* Place your application code here. */
       
        if ( Burstfin_1_Read( ) ) {                                // Last serial burst initiated finished ?
           
            Burstctrl_1_Write( 1 );                                // Clks for bit cntr and SR halted
            ShiftReg24_1_Stop( );                                // Stop 24 bit serial register
            ShiftReg24_1_WriteRegValue( 0x005555 );                // Reload 24 bit serial register
            ShiftReg24_1_Start( );                                // Re-Start 24 bit serial register

            Burstctrl_1_Write( 0 );                                // Start burst again
            CyDelay( 1 );                                        // Delay for debugging, not needed in final version
        }

    }
 

   

 

   

 

   

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ETRO_SSN583
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Last post on this. I missed fixing a warning, and did not see any need to shut off

   

74HC595 clocks.

   

 

   

Set Cnt24clks to one shot

   

Set Burstfin to sticky

   

SetBurstctrl to sync

   

 

   

#include <project.h>

int main( void ) {

    CyGlobalIntEnable;
   
    Burstctrl_1_Write( 1 );                                        // Force bit cntr and clks to SR to stop
    ShiftReg24_1_Start( );                                        // Startup the SR
    Cnt24clks_1_Start( );                                        // Starup the counter
    Burstctrl_1_Write( 0 );                                        // Force bit cntr and clks to SR to start

    for(;;)
    {
       
        if ( Burstfin_1_Read( ) ) {                                // Last serial burst initiated finished ?
           
            Burstctrl_1_Write( 1 );                                // Reset Cnt24clks
            ShiftReg24_1_Stop( );                                // Stop ShiftReg24
            ShiftReg24_1_WriteRegValue( 0x555555 );                // Reload ShiftReg24
            ShiftReg24_1_Start( );                                // Re-Start ShiftReg24
            Burstctrl_1_Write( 0 );                                // Start Cnt24clks again
//            CyDelay( 1 );                                        // Delay for debugging, not needed in final version
        }
    }
}

   

 

   

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Anonymous
Not applicable

i trying do a led cube by light up the led and light movement. 

   

 if i using PSOC 4 does it same way ...

   

any idea

   

please help me .,,

   

.thanks you very much

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ETRO_SSN583
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You need to provide a little more info -

   

 

   

1) How many leds / face of cube ? RGB LEDs or single color ?

   

2) What are you using to drive the specific LEDs ?

   

3) Current requirement of LEDs

   

4) Is each face of cube one serial array of LEDs ?

   

5) What determines pattern of LEDs on the face of the cube ? How many

   

patterns ?

   

6) Color, how many different colors ?

   

 

   

Regards, Dana.

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