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Hello I am workin on the project about the creation of Ip in vhdl to communicate avec FX3 in sync slavefifo mode.
are there any people that have already work in this part of subject to give me some advices about that or anything that can help me ?
my goal is to establish communication between FPGA(Ip) ====>FX3 (just one signle side). To do that I must use timing from sync slave fifo but this timing seems not really easy to understand.
regards,
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Hi,
The AN65974 application note has all details about the timings. FX3 and FPGA example codes are also available.
Feel free to posts if you have any questions about the details in that App Note.
Regards,
-Madhu Sudhan
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hello,
I am agree with you. I see the part about FPGA implementation Details page 43. In fact, I must use the state machine to implemented in VHDL or verilog.. isn't it ?
No probleme with that but I have questions about :
1) To join Stream_in mode, I must check the vairable MODE==STREAM_IN (page 25) but in my architecture there are not input or output call MODE, that's why I think MODE is located in the configuration of FX3
what could you say about ?
2) If I consider that the problem of MODE is resolved, I will create my code in VHDL or verilog that respect the rule give me for state machines isn't it ?
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Hi,
The MODE is only the way FPGA sends the data. You can ignore the MODE on your FPGA.
Regarding FX3, there is no issue because of this mode. Go through the FX3 firmware given with the An65974 application note and make sure that #define STREAM_IN_OUT macro is enabled in cyfxslfifosync.h file.
Regards,
-Madhu Sudhan
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Ok thanks.
But , are there any vhdl or verilog codes provide by this document about state machine ?
good week
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Hi,
The VHDL and Verilog codes for both Altera Cyclone and Xilinx Spartan FPGAs are availble in the project package with the application note.
You download the zip file in the following page. It has FX3 firmware and also FPGA Codes.
http://www.cypress.com/go/AN65974
Regards,
-Madhu Sudhan
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Ok. Thanks you