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HI,
I have a problem with ADC - DAC conversion, I am getting a signal in the input of ADC and don't get any signal at the VDAC output
1. If there any option to check where is the failure? to check if the data passed the ADC ? I know how to check the analog parts but don't know hot to check the digital...
2. Any idea? wrong C code maybe?
Thanks
Solved! Go to Solution.
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PSoC 3
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I would start by configing the A/D the same as the example project Filter_ADC_VDAC in
Creator. Thats 8 bit.....
Then take a look at this (AN61102 in particular) -
http://www.cypress.com/documentation/application-notes/an52705-psoc-3-and-psoc-5lp-getting-started-d... AN52705 Getting Started with DMA
http://www.cypress.com/documentation/application-notes/an84810-psoc-3-and-psoc-5lp-advanced-dma-topi... AN84810 PSoC® 3 and PSoC 5LP Advanced DMA Topics
http://www.cypress.com/documentation/application-notes/an61102-psoc-3-and-psoc-5lp-adc-data-bufferin... AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA
http://video.cypress.com/video-library/search/dma/ Videos on DMA
https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)
Regards, Dana.
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I would start by configing the A/D the same as the example project Filter_ADC_VDAC in
Creator. Thats 8 bit.....
Then take a look at this (AN61102 in particular) -
http://www.cypress.com/documentation/application-notes/an52705-psoc-3-and-psoc-5lp-getting-started-d... AN52705 Getting Started with DMA
http://www.cypress.com/documentation/application-notes/an84810-psoc-3-and-psoc-5lp-advanced-dma-topi... AN84810 PSoC® 3 and PSoC 5LP Advanced DMA Topics
http://www.cypress.com/documentation/application-notes/an61102-psoc-3-and-psoc-5lp-adc-data-bufferin... AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA
http://video.cypress.com/video-library/search/dma/ Videos on DMA
https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)
Regards, Dana.
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Thanks for the topics.
Right now running the ADC DMA VDAC project ( example)
But it worked well for me I just changed the input stage up to ADC....
Thanks
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Thanks for the topics.
Right now running the ADC DMA VDAC project ( example)
But it worked well for me I just changed the input stage up to ADC....
Thanks
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Fixed the problem by without the digital filter
Is there any ways to construct stable filter BP 10-200 Hz with Fs = 48000?
Visualy the filter is LP not BP...
thanks
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Not quite sure what your remaining issue is. Digital filter will create a working bandpass. Only difficulty I can think of is to send that data to the VDAC because filter delivers signed ints (with negative values) and VDAC only accepts positive unsigned values. So a conversion is needed.
Bob
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Hi Bob,
If I input to the filter only positive values it still will deliver signed negative values? can you please explain me this issue?
on page 48 appears : Not designed for low-frequency or high-frequency filtering • Stay in mid-frequency range (x kHz to y kHz)
Is it really critical? I need 10-150/200 Hz filter... The psoc filter will not do the job?
Thanks
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The Arrow statement is not accurate. To do a low freq BP the approach is a two
stage filter, a LPF followed by a HPF.
Setup a two stage filter, Chan A, as follows
Stage 1 LPF
Cutoff .2 Khz
Sample rate 1Ksps
Biquad
G = 1 linear
Chebychev
Order 8
Ripple 1 db
Stage 1 HPF
Cutoff .01 Khz
Sample rate 1Ksps
Biquad
G = 1 linear
Chebychev
Order 8
Ripple 1 db
Make plot freq axis upper limit .5 Khz
The DFB example project already handles signed issues.
Regards, Dana.
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OK.
Thanks
another issue... The filter is IIR type
There is no problem with non linear phase? I learned one statement ( didn't save it) that states "There is no recommended to use IIR filter for audio signal". Do you know if it's right?
Thanks
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IIR is, in general, non linear phase, although there are design techniques to approximate
linear phase.
Given you have an 8 bit DAC you are not doing high fidelity audio work, so is linear
phase that important ? Also you stipulated 200 Hz for upper cutoff, again is audio
quality the real issue ?
Here is an example close to linear phase using Biquad, attached.
Regards, Dana.
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Thanks for you knowlage and want to help!!
You are right about the quality....
I will try it!
THANKS!!!!!
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Glad to assist.
Regards, Dana.
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The error(s) are within your DMA setup:
Look in DMA datasheet at the description of the "nrq" signal. This must be enabled in CyDmaTdSetConfiguration().
Furthermore you defined to increment source and destination addresses, but these are only registers always at the same physical addresses.
You end the DMA transfer after the first cycle, since the next TD was set to DISABLE_TD instead of using the same TD in a loop.
Bob
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Hi Bob,
Thanks for your replay!
I reconfigured it with thw DMA Wizard, now I can see the ADC output but no the VDAC input , is is constant "64"
void DMA_Config()
{
uint8 DMA_1_Chan;
uint8 DMA_1_TD[1];
DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_1_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_1_TD[0], 2, DMA_1_TD[0], TD_TERMIN_EN | DMA_1__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR | TD_AUTO_EXEC_NEXT);
CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_1_STAGEA_PTR));
CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]);
CyDmaChEnable(DMA_1_Chan, 1);
}
Have I missing something?
Thanks
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I cannot investigate deeper since I do not have got a PSoC3 right now.
I would put a delay into your main-loop to update the LCD less frequently (every half second)
Do not read from ADC in main-loop, that will interfer with the DMA, use a static var instead that holds the last value.
Check if the interrupt handler is called more than once.
Bob
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Ok.
Will try it! Thanks
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Do not read from ADC in main-loop, that will interfer with the DMA, use a static var instead that holds the last value.
Won't the arbitration handle that ? PHUB handles that issue.
Regards, Dana.
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Your easiest start would be to use the example project for ADC DMA Filter in Creator examples.
That works, and modify the filter to meet your needs. As I recall a 2 stage, LPF followed by a HPF.
Part of your issue is you have ADC running at 16 bits, take a look at this to get the right
DMA setup (AN61102) -
http://www.cypress.com/?rID=37793 AN52705 Getting Started with DMA
http://www.cypress.com/?rID=82680 AN84810 PSoC® 3 and PSoC 5LP Advanced DMA Topics
http://www.cypress.com/?rID=44335 AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA
http://video.cypress.com/video-library/search/dma/ Videos on DMA
https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)
Regards, Dana.
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Thanks Dana!
I backed to the example project but the modification causes it to strange behavior.
Thanks for the links. I exactly looks for this information from yesterday!
Thanks!
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another question:
What makes the amplification/attenuation ratio between ADC to VDAC
for example , now I entered signal (ADC vss-vdd) , and got from the VDAC attenuated signal and amplified DC bias...
I afraid I am not understanding the way it works.... very upset..
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"Do not read from ADC in main-loop, that will (vocable missing, mess up?) with the DMA, use a static var instead that holds the last value."
There was no waiting for samples ready in the code and I am really not quite sure if you read-off a value and reset any status-bits which might influence the DMA
Bob
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Hi Bob
I canceled all the ADC reading. I connected only the example project of ADC filter Vdac , and still getting strange output.
I played with the ADC parameters but stil the output signal is amplified and have deformation ...
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What makes the amplification/attenuation ratio between ADC to VDAC
Between ADC and VDAC you have a filter with a design gain in it. If I look at
your signal there is too much gain causing the stauration effect you are seeing on
the negative going rail. There is a setting in the filter for G, cut it down to start.
Looking at scope traces, green trace output ? If so how are you getting 8 V pk-pk
out of a 5V chip. Is that because your probe attenuation not set in scope ?
Regards, Dana.
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On the scope the green is out
it is <4 pk-pk ....
I checked the scope it is ok... look at the next post. I put to examples projects results
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Hold on for a few minutes, I have a mistake in project.
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There is a signedness problem. My project works for an input < 1/2 range of
A/D, otherwise itr gives the flipped signal we see. I will file a case on this to
see how the DMA should handle this.
Regards, Dana.
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Thanks a lot 🙂
I am started to feel very fool and stupid with this issue ...
THANKS!!!!!!!
Anna
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Thanks!
As a more familiar user then me, "to fix this issue" means that it will be fix in next generation or maybe any immediate solution?
The ADC Vss-Vdd range means 0-5v +- some mV , maybe any definitions changes can solve it...
Ok lets wait to the case answer.
otherwise I will change the design.
Thanks again for your help!
Anna
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I cannot open the project 😞
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It was done in Creator 3.2 SP1, maybe thats the issue.
Regards, Dana.
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Ok! will download it and try!
Of caurse inform you too 🙂
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Ok! will download it and try!
Of cause inform you too 🙂
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Just for information..The 3.2 version didn`t helped.... the problem still exist.
I fill the case to tech support... waiting