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I am using the 1msps SAR to get around 8 samples per waveform of an echoed 120khz signal. (used in material examination). It is working ok.
Unfortunately the internal DAC can only do 8 bits, so when playing the 12 bit signal back at a slower rate using the 8 bit DAC, to be used in other equipment, the loss of resolution is affecting the waveform amplitude between echo samples, as you would expect.
One possibility would be to interpolate data to play out the DAC and derive more samples. If the sample rate is computationally doubled, this would provide a stable enough signal. I am trying to wrap my mind around that one, and have not seen any C examples. I think I can do it, but I'm still a bit confused about getting the missing Y value for an X from the formulas I've seen. My brain is missing something in addition to gray matter.
The other way to do it would be to offset using 2 SAR's exactly 1/2 so that one gets one sample and 500us later the other SAR would get the other sample. I could interleave the samples and shift out the DAC. So, it leads to the following questions:
1) Any C code for interpolation I could be pointed to that is geared for getting missing DAC samples. (Linear interpolation is obvious, cosine, maybe, Levinson-Devinson sounds good)
2) Any examples of shifting the SAR's so they are offset from each other exactly half? Any luck doing the DMA in that configuration? I have DMA running, but I've found that the PSoc sometimes lays down like a sick puppy if the DMA's are too busy.
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PSoC 5LP
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The output frequency is around 20khz, (160,000 samples per second through the DAC). Based on the AN6425, it looks like using iDAC's in parallel would be best. The dithering is too slow by 20, and the ADC feedback is snail's pace (100 samples per second).
I looked on Google and could not find the Bit Flipping issue mentioned anywhere. What is that glitch, and where can I read more on it?
If I invert the clock signal to the ADC's, then I should only be 1/18mhz off between the two samples. I would expect to need a 9 clock sample delay between the two ADC's. The bit resolution loss might be acceptable. I suspect I could create a counter to delay the startup clock into the second ADC, but I want to try the easier stuff first.
I like the analog filter idea. I will look into it also.
I'm starting to understand the interpolation methods. The website at the end of the sentence helps. It explains some of the arcane terms better than I've seen before. I'm just curious how fast cosine is on the PSOC. I'll find out. http://paulbourke.net/miscellaneous/interpolation/
thank you!
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I'll look into the Digital Filter. That sounds promising.
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wsm,
At high output speed (>200 ks/sec) PSoC5 DAC shows spikes (like on picture below) every time code flips bits xxxx1111<->xxxx0000 (16 times while going from 0 to 255). At about >1Ms the noise is unbearable. Voltage output close to Vss is also saging, distorting output. Compared to PSoC5, PSoC4M DAC is better in this regards (both 8-bit).
To have 2 ADC_SAR working out-of-phase, drive samplig using soc terminal with 1MHz clock (use NOT element for ADC_2)
http://www.cypress.com/forum/psoc-5-device-programming/adc-sar-overclocking-technique
For analog output filtering look e.g into 8-order LTC1064-2, all it needs is a clock provided by PSoC.
http://www.linear.com/product/LTC1064-2
http://www.linear.com/parametric/Lowpass_Filters
Standard math sin() calculation on PSoC5 takes >1500 CPU ticks. With 12-bit sine lookup table I get ~56 ticks. At 64 MHz BUS_CLOCK and 160ks/sec all you have only 400 ticks for interpolation. It is unlikely that PSoC can make 6 multiplications on the fly that fast. Cubic interpolation is about same result. I would try Digital Filter first - it is free (no coding...)
Laslty, I have feeling that the task does not fit well for PSoC (need 2-3x faster ADC, >320kB memory to store data, and 12-bit DAC, etc.) Would it be easyer to upgrade to e.g. M4 micro?
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Thank you for the information. I think I've seen that issue with the bit flip, but due to other parameters in the system it is filtered out by the time the receiver gets it. We got lucky. Several thousand feet of wire between us and the receiver helps dramatically.
I was able to use the digital filter block, and you are correct. It does indeed do what I needed, and works well. The output amplitude drops off dramatically, but I think we can compensate.
In addition, the DAC being unsigned causes issues when paired with the signed digital filter. That causes wrap from top to bottom when using full 0-255 values for the ADC input 8 bit into the filter. Very interesting phenomenom.
We only have to deal with 2 millisecond bursts of information, and have several tens of milliseconds to process the wave form. Regardless, the DFB provides good interpolation for free.
You are right about the cpu choice. But, when the project started several years ago, it was the best low cost solution. We are doing something new, and the toolbox provided by the PSOC has more than compensated for its short comings, even with the bit flip issue. (We avoided a bullet on this one)
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I think I understand what you are talking about now on the ADC interleave.
I have been working on a jitter in acquisition of +/- 1 microsecond. So I switched my ADC to a logic controlled hard Start Of Aquisition (SOC). In that case, you would indeed use a NOT on the 1 mhz acquisition trigger clock.
Until I needed to control the jitter, I was using software start, and the signal creation started on cue due to logic.
I apologize for my previous answer. You are right, no need to delay the base clock, simply sync to the base clock and flip the 1mhz acquisition start signal.