VDAC8 output

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Anonymous
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Hi,

   

What is the output lavel of the VDAC8?

   

I am inputting ~2V P-P signal to ADC filtering it and output threw VDAC8- the output is 150mV P-P riding on ~50Hz noise.

   

Is it expectable results?

   

THANKS 

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ETRO_SSN583
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From datasheet (you may want to buffer it) -

   

Both output ranges have 255 equal steps. The VDAC8 is implemented by driving the output of the current DAC through resistors and obtaining a voltage output. Because no buffer is used, any DC current drawn from the DAC affects the output level. Therefore, in this mode any load connected to the output should be capacitive.

   

 

   

The Zout of the VDAC is 4K for the 1V range, 16K for the 4 V range.

   

 

   

I assume you are NOT connecting a 50 ohm load to it, that would not work whether or not

   

its buffered.

   

 

   

Regards, Dana.

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ETRO_SSN583
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From datasheet (you may want to buffer it) -

   

Both output ranges have 255 equal steps. The VDAC8 is implemented by driving the output of the current DAC through resistors and obtaining a voltage output. Because no buffer is used, any DC current drawn from the DAC affects the output level. Therefore, in this mode any load connected to the output should be capacitive.

   

 

   

The Zout of the VDAC is 4K for the 1V range, 16K for the 4 V range.

   

 

   

I assume you are NOT connecting a 50 ohm load to it, that would not work whether or not

   

its buffered.

   

 

   

Regards, Dana.

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ETRO_SSN583
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You did this step -

Anonymous
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Ok. understood.... and the current is low? because of it I am getting 150mV signal?

   

Ok, I will put the buffer .

   

Tel me please ....one additional issue:  the total number of the PGA and OPAMP is 4? or there is 4 OPAMP and some additional PGA?

   

Thanks

   

Anna

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ETRO_SSN583
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Total is 4 OpAmps. Each time you use a PGA it uses one OpAmp.

   

 

   

Don't forget, in some situations you can mux them, use one in a time slot fashion with different

   

configurations. Make it do multiple duties.

   

 

   

Regards, Dana.

Anonymous
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Thanks.

   

I am thinking about muxing but I need all of them on the main path.

   

Do you know any other way to buffer Vref ? This action is using 1 OPAMP for me...

   

Can I use ONLY one filter? If I need another one? I am getting a 50Hz noise on the output.....

   

Regards!

   

Anna

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ETRO_SSN583
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Possible common mode oscilloscope problem. Consider using two

   

channels, and do a differential measurement. See ap note.

   

 

   

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=9&ved=0CEUQFjAIahUKEwjovfCLhoDHAhVFooA...

   

 

   

Regards, Dana.

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Anonymous
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Thanks! very useful.

   

I am doing differential measurements and using 2 channels:)

   

but because I am new with psoc parts I have a lot of question and problems 😞

   

Thanks!

   

Anna

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Anonymous
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I attached my project.
The problem is that I am getting as an output of the VDAC8 signal that looks in very low sample rate - see example 1 pic
I connected PGA that works like buffer and amplifier , a PGA output looks very strange - example 2 pic
After removing the caupling capacitor ( C3) from the PGA output I getting something like square wave - example 3 pic

   

change the PGA to OpAmp follower problem 2+3 not relevant but the output still strange. - example 4 pic

   

PLEASE HELP!
I have no Idea how to solve it....

   

Thanks!!!!! Anna

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ETRO_SSN583
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Some observations -

   

 

   

1) You load the output of PGA1 with 1 uF, Thats not a good idea, the phase margin

   

would lead potentially to oscillation, at minimum severe ringing.

   

 

   

2) Your VDAC range is 0 - 4 volts, PGA1 G = 16, so you are asking for 64 volts

   

out of PSOC. The PGA should be set for a G = 1, in fact just use an OpAmp configed

   

as a buffer. PSOC can only produce an analog signal that ranges from Vssa to Vdda.

   

 

   

3) In the Piezo path you have 10 uF polarized caps, and very high fdbk and input R's.

   

Electrolytics are fundamentally leaky capacitors, and that leakage x the fdbk and input

   

Rs will create large offsets. To maintain large Zin either replace caps with MLC

   

ceramics or DC couple the path and eliminate the caps.

   

 

   

Regards, Dana.

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Anonymous
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Hi,

   

1. I replaced the PGA with OPAMP follower. The capacitor at the feedback prevents the amplification of the DC that the AC ride on it BUT makes deformations on the signal. I can measure the output of the PGA/OPAMP with the oscilloscope without a cap?   

   

2. I doesn`t get 0-4V from the VDAC, I have ~ 130mV , because of it I made GANE=16 

   

3. I put the ceramic capacitors, but still have a lot of noise. 

   

What do you mean DC couple?  I can? I have an AC input signal and AC output.

   

4. I read a LOT of material about noise on ADC DAC path , you sent me  and I made a lot google but still I don`t have any Idea how to rid off the noise of the VDAC output without filter.

   

I tried to change the sample rate and the input signal...nothing works...

   

You are helping me a lot!!! Thank you very much!

   

I very grateful to you and doesn't have enough words to express my apriciation!

   

Anna

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ETRO_SSN583
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1. I replaced the PGA with OPAMP follower. The capacitor at the feedback prevents the amplification of the DC that the AC ride on it BUT makes deformations on the signal. I can measure the output of the PGA/OPAMP with the oscilloscope without a cap?   

   

Yes, the scope is a Hi Z in, if using 10X probe its 10 Mohm Z, 1X probe 1 Mohm.

   

 

   

2. I doesn`t get 0-4V from the VDAC, I have ~ 130mV , because of it I made GANE=16 

   

One way to get the G is do it in the filter settings, then you can just use a OpAmp buffer

   

instead of PGA. If that is not workable what is the offset out of the Vdac with no signal

   

in ? And what are you attaching to the PGA ref pin (other than the cap).

   

 

   

3. I put the ceramic capacitors, but still have a lot of noise. 

   

What do you mean DC couple?  I can? I have an AC input signal and AC output.

   

DC couple means a DC path, eg no capacitors in the signal path.

   

Your Vdac output signal, what is it being sent to ?

   

The ceramic caps are to eliminate leakage which would cause offset in the input stage.

   

Any leakage goes thru R 8 and R7, and would cause OpAmp3 to move off its bias point.

   

 

   

4. I read a LOT of material about noise on ADC DAC path , you sent me  and I made a lot google but still I don`t have any Idea how to rid off the noise of the VDAC output without filter.

   

If you ground P1_32 what does the noise look like ? If its still present then you have coupled

   

noise in you prototype to some parts of the signal path. If its gone then Piezo wiring picking up

   

noise.

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ETRO_SSN583
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So first adjust the G you want in the input stage OpAmp.

   

 

   

Then adjust the A/D buffer G to get the maximum dynamic range or signal

   

for the peak signal in. A starting point is you had the intermediate OpAmp

   

stage set to a G = 3, the A/D buffer gain has an option of 4, start with that.

   

 

   

Note I changed the opamp names so you would need to change API names used.

   

 

   

Regards, Dana.

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ETRO_SSN583
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Keep in mind the connections from Piezo to PSOC should be shielded cable or

   

a twisted pair, to minimize pickup from AC powerlines in room or other interference.

   

 

   

Evaluate one stage at a time to work out signal issues. So start by looking at

   

OpAmp 3 output, are you satisfied looking at the signal there.

   

 

   

I think you can eliminate an opamp and make things simpler by taking

   

G in the A/D buffer configuration.

   

 

   

 

   

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ETRO_SSN583
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A/D setup -

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ETRO_SSN583
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I know this may be frustrating, I am handicaped w/o a Piezo here. But idea is to implement the

   

circuit show in the attached TI ap note. Normally the output would go to the A/D. But you had

   

2 Gs in your circuit, input G of 2 followed by a G of 3. PSOC A/D has a buffer in its front end

   

that can have a G up to 16, so that could eliminate all signal path opamps.

   

 

   

I cannot try this because I am at a remote location, and no piezo.

   

 

   

Just a thought.

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ETRO_SSN583
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And this would be schematic -

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ETRO_SSN583
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Here is an experiment I ran that looks promising. Some questions, observations -

   

 

   

1) What freq range do you want out of the Piezo ?

   

2) Are you using digital filter to get rid 60 Hz, now its setup as BP, it should be band stop.

   

3) You might consider conditioning Piezo physically close to the unit with a simple JFET buffer.

   

That would help your 50/60 Hz problem.

   

4) Another approach to 50/60 hz rejection is to use a diff amp, G = 1, and feed one input

   

with Piezo, the other with trimmed 50/60 Hz signal, and subtract it out.

   

5) Another approach to eliminate is to use charge amp, that may take out 50/60 Hz pickup.

   

 

   

Regards, Dana.

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ETRO_SSN583
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Here is a look at scope result, single shot event, tapping the Piezo, blue trace

   

filtered by scope, 4V pk-pk, high pass, 250 Hz. Removes most of the 50/60 Hz component.

   

 

   

So A/D would actually see (its G = 8 vs PGA at 50) a .75 V signal., more than enough in the

   

scheme of things.

   

 

   

Regards, Dana.

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ETRO_SSN583
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Here are some notch filters for power line work should you chose not to

   

use digital filter approach -

   

 

   

Regards, Dana.

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ETRO_SSN583
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Here is an idea that may have some merit. Basically it forces the AC Line

   

interference to be common mode by virtue of the fact the connections to the

   

Piezo would be roughly equal, wire length, layout, etc.. Because the interference

   

is now common mode the A/D diff front end rejects it. You would set A/D up for

   

diff mode, internal Vref 1.024 V, Buffer G = 8, input range 1.024V +/- 1.024V for

   

for starters. The last can be reduced which increases the sensitivity, but trades off

   

that increased resolution/sensitivity for range.

   

 

   

The bias network biases up both inputs to Vdd /2. Note the R's should be in final

   

application 1% or better as they would affect the conversion of the line AC signal

   

interference to common mode.The Z load presented to each side of the Piezo should

   

be equal to force the noise pickup to be ~ same magnitude. !% R's, all other things

   

being equal, would yield ~ 40 db CMR, .1% 60 db CMR.

   

 

   

Note if you are only using the A/D and Filter to get rid of the noise you could eliminate

   

them and use 3 OpAmps to create an Instrumentation Amplifier (IA) and accomplish the same

   

result rejecting the common mode line interference. You would need a precision external

   

IA thin film network to implement good CMR. Or external IA.

   

 

   

Regards, Dana.

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ETRO_SSN583
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The last post, the diff mode completely eliminates 50/60 Hz, unless I

   

purposely unbalance the hookup wires connecting the Piezo. Now I am

   

trying to eliminate the DFB block and just use the A/D and VDAC, given

   

DFB no longer needed (you have to confirm it was just for 50/60 Hz filtering).

   

 

   

Regards, Dana.

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ETRO_SSN583
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Piona, here is a project that seems to work quite well.

   

 

   

The scope shot, yellow VDAC out, purple Scope LPF at 10 Khz to remove sample noise.

   

 

   

Regards, Dana.

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Anonymous
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Waw!!! Dana you are grate!!!! Thanks so much! you gave me so many points to view ! I am going to try 🙂

   

Will inform 🙂

   

THANKS THANKS THANKS   !!!

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ETRO_SSN583
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Piona, fatal flaw in my design. I thought the mic I was using was electret.

   

Its voice coil, so intrinsically has much more output than electret. So this

   

may not work for you. Try it, set A./D buffer G to 8, and start with the smallest

   

range setting, I think its ±0.064 V, (–Input ± Vref/16).

   

 

   

Regards, Dana.
 

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ETRO_SSN583
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There is one other possibility, there are electret mics that have JFETs embedded in them

   

to translate the HiZ to low Z for driving cables. This has the side benefit that AC line

   

pickup now is confined to the head, not the long runs of wire/cable, So that's another way

   

of beating the HiZ layout susceptibility to noise pickup. Panasonic makes parts like this.

   

 

   

Regards, Dana.

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Anonymous
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Dana Hi,

   

I made a mix with all the possibilities and your sugestions:)

   

1. I decided to input the piezo mic trow JFET buffer - ordered some Jfet transistors tomorrow will get them

   

2. It is impossible to me to amplify the signal in the ADC  because I have shifted signal to 2.5 DC to get only positive values in the ADC input ( the original piezo output is AC around zero), and the ADC amplifies the DC as well.

   

3. I need the digital filter  to choose some specific freq,

   

4. In my current design I don`t have 50-60Hz interference and I am happy 🙂

   

BUT I am getting at the output all the harmonics of the input signal

   

I put LPF ~ 500 HZ before the ADC to rid off high freq noise and to reduce the ADC sample rate - still have all the harmonics

   

In the pic: 80Hz sinus input 

   

Where the harmonics created?

   

  

   

   

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Anonymous
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Hope you can see the pictures in previous post if not attached there

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ETRO_SSN583
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Can you do the FFT with log based Y axis ?

   

 

   

A/D, bypass the input buffer, and observe the improved range you will

   

get to Vssa and Vdda.

   

 

   

Regards, Dana.

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Anonymous
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Sure 🙂  FFT log attached 🙂

   

I am using Vssa-Vdda as an input range...

   

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Yes, your range was selected as Vssa to Vdda, but if you look at the graphic of range in the
config window, its not quite Vssa to Vdda.

   

However if you bypass the input buffer you actually get a range > Vdda and < Vssa.

   

And the graphic of range in the configurator will show that.

   

 

   

Your graph, the idea is to get 20log( x ) on the y axis, decibel voltage plot.

   

 

   

Regards, Dana.

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ETRO_SSN583
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Piona, one comment on the JFET buffer. Typical approach is to use a high Z R from Gate to

   

ground to allow bias developed in source resistor to the gate. The limit on this Rgatetognd is

   

gate leakage and the resultant shift in bias point that would occur. So check datasheet for

   

Ileakage, hot.

   

 

   

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CB4QFjAAahUKEwjAsOmi6pHHAhXMmoA...

   

 

   

Regards, Dana.

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Anonymous
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Hi Dana,

   

The buffer I made:

   

   

 

   

The simulation:

   

   

   

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Anonymous
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R10 - I put a pot-trimmer and can adjust the bias point.

   

at this moment I tested it and connected the psoc.

   

Now I need a analog filter before ADC 

   

1. To sample the signal in relatively low SR- more precise digital filters can be programmed 

   

2. I am sampling all the WN that consist and its aliasing in the signal.

   

Any Idea for good LPF biasing? with narrow pass band?

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ETRO_SSN583
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Some thoughts -

   

 

   

1) R6 & R8 for a voltage divider at input, hence throw away gain needlessly ?

   

Loss of 20db....Is R6 C4 inside the piezo ?

   

 

   

2) 10M should be OK, but datasheet does not show gate leakage hot, so that

   

should be looked into in light of the fact its going to flow thru the 10M and cause

   

a bias point shift.

   

 

   

3) For no signal in you should have ~ 2.5 V source to ground bias point.

   

 

   


4) R7 is for ?

   

 

   

5) You chose an RF JFET, any particular reason ?

   

 

   

6) JFET handing on production floor, and in prototype, small signal JFETs have

   

very small diffusion geometry, so real easy to damage gate region, leakage,

   

etc. with ESD.

   

 

   

Regards, Dana.

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Anonymous
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Hi,

   

1. R6 and C4 is modeling the piezo.

   

2. the real transistor I used: 2N5457 , but it doesn`t have a spice model. but in real works properly ( looks like:))

   

3. yes for no signal I am getting DC ~2.5V

   

4. R7 is to avoid direct signal to gate - protector

   

5. see 2

   

6. This one JFET I bought in TO92 package 

   

 

   

Thanks!!

   

Anna

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