Below are the details of the 65nm 144M QDR family of SRAMs.
The tentative schedule for availability of these parts is June 2011.
Please contact your local Cypress sales representative for availability of the specific options you are interested in.
I'm just laying out a PCB using four sites, either CY7C1520KV18 or CY7C1620KV18 (when available) and would like to "future proof" my design by connecting up the address pad for a possible 288Mb device. Has a pin been allocated for this yet?
These RAMs are to replace fast SDRAMs, which have 51 ohm terminators on all lines.
Would the fast SRAMs benefit from having all the signal lines terminated? The RAM chips are all fed from a single FPGA.
Thank you for your consideration.
Unfortunately, JEDEC has not defined the address expansion pin for 288M density for these devices CY7C1520KV18 and CY7C1620KV18 devices both of which are DDR2 Burst 2 x36 configuration.
Would you be able to use a x18 bus width device instead.
For the x18 bus width option for the DDR2 Burst 2 x18 configuration (CY7C1618KV18 and CY7C1518KV18), address expansion pin for the 288M density device is defined which is ball B5.
Cypress offers device with On Die termination which can eliminate the need for external resistors for termination.
For the 72M device, the ODT part number would be CY7C25702KV18 device.
Please let me know whether this answers your questions.
This is a question for DougE
You mentioned that you are replacing high speed SDRAM with the newer SRAM.
what specific feature of the SRAM is influencing your decision? speed or Random Transaction rate ?