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Hi,
My requirement is to output data in microseconds, and I am using many timer interrupts to achieve it in my code. The result is unexpected jitters in the o/p. It's definately not a good approach to have implementation inside ISR's, however i cannot think of anything else to achieve this timing. Any suggestions ??
Note : The max tolerance allowed in the system is 2us. (Simple function execution take 1us)
HW : PSOC5LP, Creator 3.0
Screenshot : 5 timers are being used, Timer_Period_0 works fine, but Timer_Period_1 has varying intervals of 496, 504, 496, 504. I am not able to understand this behavior. Any help will be highly appreciated.
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PSoC 5LP
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Can you post your project or at least describe functionality of
timers and what ISR is doing in a little more depth ?
“File” Creator
“Create Workspace Bundle”
Regards, Dana.
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Assuming a core clock of 80MHz, 1µs granularity / accuracy means just 80 clock cycles. Thats not much. Probably you want to use a hardware-based solution.
The jitter you see might stem from the fact that the second timer ISR has a lower priority than the first, so it can only run when the first one isn't.
Maybe you should explain a little bit more what you want to achieve.