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I am just beginning to use PSoC 4. I would like to have 6 PWM outputs or more from CY8CKIT-042 PSoC 4 Pioneer Kit. When I try to use 6 TCPWM blocks together with 2 interrupts (overflow and compare events) for each block to toggle logic levels on 6 digital outputs, I get error that only max of 4 TCPWM blocks are allowed. I also tried the UDB based PWM blocks, but got errors like only max of 4 datapaths were allowed. Is there an alternative solution without resorting to pure bit-banging? Thanks.
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Welcome in the forum, Diode!
You can use the 4 TCPWMs and 2 UDB-based PWMs with 16 bit width. When in need, you can use the two-outputs-mode of the latter giving you 8 PWMs in total or saves you 2 TCPWMs for other uses.
Bob
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Thanks Bob. Your advice works.
I also have a different question on the interrupt handling of PSoC 4. When using 4 TCPWM blocks with the same clock source and 8 interrupt handlers (4 for overflow, 4 for compare), I find they work without glitches when all compare counts are set to the same, meaning 4 interrupts can occur at the same time. From this post, ARM Cortex M only has 1 bit for pending status per interrupt source. Does that mean those 4 TCPWM blocks interrupts are actually registered as different sources? Or am I missing something? Thanks.
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The only key drawback of the dual mode PWM use is the component shares
a common clock, the Tc output and its interrupt shared, otherwise functions as
two independent PWMs.
Regards, Dana.
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For a PWM component the interrupt sources are internally ORed and the result is the interrupt signal which you usually connect to an isr-component. Within the interrupt handler ypou can / should analyze the cause and act accordingly. Same goes for the TCPWM, only that the available internal sources for generating the interrupt are fewer. Do not forget to reset the interrupt cause within the handler, usually done by reading the component's state.
Bob
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For a PWM component the interrupt sources are internally ORed and the result is the interrupt signal which you usually connect to an isr-component.
This is within the specific SCB block, eg. all the block interrupts are ORed, but the other blocks have
their own ISR domain.
Regards, Dana.