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Hi,
I'm trying to implement an 8-bit SPI slave on PSoC 3/5 and use the 4-byte hardware FIFO. According to the data sheet, since I have CPHA==0, I must write directly to the shift register using SPIS_WriteTxDataZero() for the first outgoing byte. How does this operation affect the FIFO? In other words, if I have an empty Tx FIFO and then write via SPIS_WriteTxDataZero(), is the FIFO still empty? If so, can I fill it up using 4 SPIS_WriteTxData() operations before the first data clock edge is even received?
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PSoC 5LP
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I would not fix to a FIFO depth of 4. There are PSoCs that have got a 16 level deep FIFO. You can always query the component for FIFO full.
Writing directly into the transfer register does not occupy a FIFO entry.
Bob
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Bob,
Thanks for the info.
Paul