two type datapath in cihp ?

[Anonymous]

Hi:

   

I just noticed in datasheet, there are two types of datapath, one in UDB, the other in DFB. Is that correct?  Obviously the two 'types' datapath are not the same architecture,  different ALU input selection, RAM size, output pipeline...and so on.

   

It seems the datapath configure tool is to configure the UDB datapath only, is that correct?   I can not find any tool to help customized design on DFB datapath.

   

Thanks.

   

B.R

[Anonymous]

Hi Schurtz,

       

Yes, the datapath for UDB is different from datapath of DFB. The datapath Configuration tool is used to configure the UDB datapath.

   

Tool to customize DFB datapath is currently not available. This might be available in future.

[Anonymous]

Thanks,DASQ.

   

Another, in TRM, D0,D1 can be written from FIFO, but I can not find the D0/D1 WR source item in datapath confiure tool, so how could I configure the dynamic configuration as load D1/D0 from F1/F0 ?

   

Is the the shift operation asynchronic logic or DP clock latch register?  I want to make clear shift operation is based on current ALU output or previous registered data.  And whether it is the same about the A0/A1 written operation from ALU / shift?

   

Thanks very much.

   

B.R

[Anonymous]

Hi Schurtz,

       

The shift operation is synchronous with DP clock.

   

The D0/D1 WR source item is not available in the datapath configuration tool. I'll look into the register map and see if it is possible to load D0/D1 with F0/F1.

[Anonymous]

Hi DASG:

   

Thanks for updating any information on FIFO to D reg  loading.

   

I got another question:  carry_in input port is available in base cy_psoc3_dp module only.  If I use cy_psoc3_dp8, and configure the CI_selection as ROUTE, how it works, since there's no port to connect with external signal?  Or should it be forbidden...

   

Thanks.

   

B.R

[Anonymous]

Hi:

   

About the FIFO to D reg loading,  I find the answer in PSoC creator 212,it's controlled by outside loading signal. So you can forget this question.  I'm still looking for carry in route question's answer.

   

Thanks.

   

B.R 

[Anonymous]

Hi Schurtz,

       

If you are using cy_psoc3_dp8 then .route_ci(1'b0) should be changed to accomodate the external signal.

   

Replace the (1'b0) in bracket with the name given to the terminal (input or output) that appears on the component symbol.

   

For example .route_ci(name), where 'name' is the signal which has to be routed.

           

Regards,

   

dasg

[Anonymous]

Ok, I misunderstood on different modules.  I just noticed carry_in / carry_out siganl .ci / .co in base cy_psoc3_dp. 

   

So, I guess the .ci/.co actually become carry_in from REGIS as configuration tool item for CY_PSOC3_DPx, and if I use the base cy_psoc3_dp, I have to connect .ci & .co extenally for carry, i.e in multi-bytes adding.  is that correct ? 

   

Question 2, if I configure the status register as interrupt mode, as TRM declared, only the low 7bits can be connected from the INT source, my understanding, the status MSB = | (status[6:0) & mask[6:0]), then the MSB route out as UDB IRQ to an IRQ MUX.... am I correct ?

   

So, any UDB IRQ to a MUX, is actually fixed from status MSB ?  Or, any route instruction can be referenced for UDB IRQ source?

   

Thanks.

   

B.R

[Anonymous]

 Hi Schurtz,

   

.ci and .co signals can be used in REGISTERED carry mode or CHAINED carry mode. In REGISTERED carry mode, the .ci and .co would connected together, whereas in CHAINED mode the .co output signal of the LSB datapath should be connected to the .ci input signal of the MSB datapath for multibyte operations.

   

When status register is configured in interrupt mode only lower 7 bits are used for masking. The MSB will be routed out to interrupt controller via IDMUX. As you say the MSB will be a '1' if status[6:0]&mask[6:0] is non - zero. The MSB will routed as UDB level interrupt.

   

Any signal generated in UDB can be a source of IDMUX. The datapath conditional outputs for eg: PWM output can be a source of interrupt and it will not go through status register. UDB generated signals will be mostly used as edge/pulse interrupts whereas the status register interrupt is used as a level interrupt.

   

Hope this answers your queries.

   

Regards

   

Anup