The jitter transfer characteristic is that of second order low-pass filter with the -3dB point at approximately 1.5MHz. This means that if the jitter frequency is less then than loop bandwidth, it will pass through the PLL and appear on all outputs. Otherwise the filter will attenuate the jitter at the rate 20dB per decade. The cycle-to-cycle jitter of REF is really high frequency, it will be greatly attenuated. The primary causes of cycle-to-cycle jitter for the output are power supply noise on PLL's supply inputs and random thermal the mechanical noise. So there is no spec for the input REF cycle-to-cycle jitter. If it is less than then 300ps for the REF input cycle-to-cycle jitter, it will be fine. If the input clock with 2ns cycle-to-cycle jitter, the ZDBs (CY23xx) like CY2308 or CY2309 for example would not lock. If the input clock has 2ns low frequency jitter (much lower than 1.5MHz), the ZDBs will keep lock and keep the cycle-to-cycle jitter 200ps. But the output will track the input low frequency jitter. The period jitter will be close to 2ns.