Please create a tech support case (MyAccount -> MyCases) so that one of our engineers can look into this.
Were you able to get this problem sorted. I have a similar problem that when I transfer data over EP2 in slave fifo mode and then do control transfers over EP0, the data transfer over EP2 eventually fails. I've hooked up an analyser and just before EP2 transfer fails a control transfer has taken place - after this EP2 returns an NRDY signal and no more data is transferred over EP2.
Could you please share your source code that is giving the above mentioned issue.
I was able to get my data transfer problem sorted out by replacing the FX3 engineering sample part with a production part. I have replaced this part on three different boards and now no longer see any issues with the data endpoint or control endpoint stalling. I carried out tests with applications that used either the Cypress or Libusb driver. Strangely the Libusb test would not work until I had disconnected the 32KHz oscillator.
I have also recently started seeing this same issue which occurs after many reads and writes on the EP0. While using EP0 I am also using the 32-bit GPIF at full speed. The stall happens on this function call CyU3PUsbSendEP0Data(uint16_t count, uint8_t * buffer); Returns Error Code 72 which I believe is CY_U3P_ERROR_ABORTED. The FX3 has the following markings:
I am also openning up a case for this issue.
Thanks in advance.