Using SIO ports on PSoC LP5

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Anonymous
Not applicable

 Using SIO ports on PSoC LP5.

   

It appears all SIO ports (port 12) are used for LCD. Is this correct?

   

Underlaying issue:

   

Have an analog signal 0.45V-4.54V as input to AD converter, and AD converter range is set up to 0V-6.144V

   

AD converter will not see anything above 3.354V. works fine below this voltage.

   

Please advice.

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Bob_Marlowe
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No signal on a pin may exceed VDDD or VDDA. In your case it seems that your power is 3.3V

   

 

   

Bob

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HeLi_263931
Level 8
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What kit are you using? Normally, the LCD is connected to P2[0..6], so P12 should be free. But even then Bob is right: analog voltages are not allowed to exceed the analog supply voltage (Vdda). If you need that, use a voltage divider.

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ETRO_SSN583
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When you open ADC properties window you will see a graphic to right

   

that shows allowed range at ADC input -

   

 

   

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Anonymous
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1.  The datasheet specifies max input on analog pins in high Z mode as 5.5V. Is the datasheet wrong?

   

2. The AD converter is configured to have a range of 0-6V. That is obviously not the allowed range. Do I or you misunderstand?

   

3. As you can see, None of the P12 ports are available for use as analog pin. Maybe I am missing something.

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Anonymous
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 img attached

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ETRO_SSN583
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1.  The datasheet specifies max input on analog pins in high Z mode as 5.5V. Is the datasheet wrong?

   

Datasheet correct, what you are seeing is the parasitic diode turnon on pins inherent in CMOS.

   

 

   

2. The AD converter is configured to have a range of 0-6V. That is obviously not the allowed range. Do I or you misunderstand?

   

It is a tad confusing. What you are really dealing with is actual HW limits of pins and effective G

   

or slope of a choosen reference in V/LSB of the ADC. Compounded by ADC buffer effects, which

   

in one case they call R-R but its actually not R-R.

   


   

3. As you can see, None of the P12 ports are available for use as analog pin. Maybe I am missing something.

   

 

   

Not sure whats going on here......

   

 

   

Regards, Dana.

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Anonymous
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time for a Cypress support case!

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Anonymous
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... what you are seeing is the parasitic diode turnon on pins inherent in CMOS. (Dana)

   

Not sure what you are talking about here. datasheet allows the voltage on the pin to go above VDDIO, and over 5.5V

   

 

   

 

   

..It is a tad confusing... (Dana)

   

Not really confusing at all. You are just not understanding. The range of the AD does not give the allowed input voltage

   


   

 

   

...Not sure whats going on here...... (Dana)

   

 

   

Exactly

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Anonymous
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1    The SIO can be used as analog input to a compartor

   
          2.          From data sheet section     6.4      I/O System and Routing   
   
        
   
     Additional features only provided on SIO pins:   
   
          No analog input     , CapSense, or LCD capability   
   
        
   
     3. Compare figure 6-8 and 6-9, you can see that the analog section is missing on the SIO. That would explain why P12 is not list as ananlog input in the creator pin selection menu.   
   
        
   
     That may be the problem with your configuration   
   

However, it may be best to ask Cypress if you still want to use it for your applicaiton

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Bob_Marlowe
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An answer to your question #2

   

2. The AD converter is configured to have a range of 0-6V. That is obviously not the allowed range. Do I or you misunderstand?

   

Since the ADC can operate at different Vref settings there is an explanation on page 9 in the datasheet that tells that the 6V mode can be used to measure the supply voltage. Furthermore it is stated that the input may not exceed max electric input range.

   

 

   

Bob

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ETRO_SSN583
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..It is a tad confusing... (Dana)

   

Not really confusing at all. You are just not understanding. The range of the AD does not give the allowed input voltage

   

 

   

That range of +/- 6Vref is the slope gain of the A/D, its not actually the "range". The actual

   

range of measurement is a f() of not only A/D but all signal path characteristics. In the case

   

of CMOS components there are diodes attached to the input pin, that turn on when

   

Vssa - Vth>= Vin >= Vdda + Vth where Vth is the threshold of the parasitic diode, ~ .5 to

   

.7 V.

   

 

   

The +/- 6Vref is telling us that if we have the A/D set to 16 bits, then the slope of its

   

transfer function is 2 x 6V / 2**16, or ~ 183 uV /lsb.

   

 

   

So the slope and ref settings can indicate a large "range" potential, but thats not the only thing in the

   

signal path.

   

 

   

 

   

Regards, Dana.

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ETRO_SSN583
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With regards to CMOS inputs and parasitics, just google it, many references.

   

 

   

    

   

          http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CCUQFjAB&url=http%3A%2F%2Fwww.an...

   

 

   

Regards, Dana.

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Anonymous
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 Daanak,

   

Enough. please do not contribute to this thread

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Anonymous
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 H L,

   

thanks.

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