3.3V IO voltage with external regulation mode with PSoC5LP

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Anonymous
Not applicable

I would like to use external regulation mode where 1.8V is applied directly to VccA and VccD, while also operating the VddIOx at 3.3V (or greater)

   

However, the datasheet states (sec 6.2 Power System) that in this case, VddA and VddD *should* be connected to VccA ad VccD.   If this is done, it then seems that VddIO *must* be connected to 1.8V, correct?

   

What happens if VddD and VddA are instead connected to 3.3V?  Is it possible to disable the votlage regulators?

   

My design needs 3.3V IOs - is it possible to use external regulation?

   

TIA,

   

Chris

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1 Solution
himam_31
Employee
Employee
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Hello ,

   

The VDDX pins must be tied to their respective VCCX pins, but do not power the VCCX pins with VDDX-level voltages such as 3.3 V or 5.5 V, or the device may be damaged. So you cannot have VDDIO powered at 3.3 and VCCx supplied with a 1.8V.

   

This is mentioned in the "Unregulated Mode" of the document "PSoC® 3 and PSoC 5LP Hardware Design Considerations" Link:http://www.cypress.com/documentation/application-notes/an61290-psoc-3-and-psoc-5lp-hardware-design-c...

   

Thanks,

   

Hima

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ETRO_SSN583
Level 9
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From the TRM -

   

 

   

> 15.3.1.1 Internal Regulators
For external supplies from 1.8 V to 5.5 V, regulators are
powered and the supply is provided through the Vddd/ Vdda
pins. An external cap of ~1 µF is connected to the Vccd and
Vcca pins.

   


For the 1.71 V < Vcc < 1.89 V external supply, power up the
device with Vccd/Vcca pins. In this mode, short the Vddd pin
to Vccd and short the Vdda pin to Vcca. The internal regula
tor remains powered by default. After power up, disable the
regulators, using the register PWRSYS.CR0 to reduce
power consumption.

   

 

   

http://www.cypress.com/knowledge-base-article/connections-vcca-and-vccd-pins-psoc-3-and-psoc-5lp-kba...

   

 

   

Regards, Dana.
 

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ETRO_SSN583
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Control Registers for PSOC 5LP from register TRM.

   

 

   

Attached.

   

 

   

Regards, Dana.

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rola_264706
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Here is the Data sheet for the PSOC 5lp. See section 6.2.2  and how to power a device that needs a higher voltage such as an LCD see figure 6.7. http://www.cypress.com/file/45906/download.

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ETRO_SSN583
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The datasheet is not clear on disabling the regulators and supply power externally for

   

1.8 V operation and external with external I/O ring at another voltage. I recommend

   

you file a CASE (and post back results for forum benefit) -

   

 

   

To create a technical or issue case at Cypress -

   

 

   

www.cypress.com

   

“Support”

   

“Technical Support”

   

“Create a Case”

   

 

   

You have to be registered on Cypress web site first.

   

 

   

Unless I/O ring an isolated well design I am guessing we cannot do this.

   

 

   

Regards, Dana.

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ETRO_SSN583
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One quick check (still need CASE to confirm) is to run part at 1.8, and take

   

a 1K R in series with your desired I/O supply and probe that to one I/O domain

   

and look at Vddio voltage at the pin. If its non isolated the Vddio will clamp

   

somewhere around 1 - 2 diode drops of 1.8, that is 2.5, 3.2.

   

 

   

Regards, Dana.

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himam_31
Employee
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Hello ,

   

The VDDX pins must be tied to their respective VCCX pins, but do not power the VCCX pins with VDDX-level voltages such as 3.3 V or 5.5 V, or the device may be damaged. So you cannot have VDDIO powered at 3.3 and VCCx supplied with a 1.8V.

   

This is mentioned in the "Unregulated Mode" of the document "PSoC® 3 and PSoC 5LP Hardware Design Considerations" Link:http://www.cypress.com/documentation/application-notes/an61290-psoc-3-and-psoc-5lp-hardware-design-c...

   

Thanks,

   

Hima

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Anonymous
Not applicable

Thank you all.  I've been all over the datasheet - and was just hoping that there was a way to reconcile page 1 features :

   

Voltage range: 1.71 to 5.5 V, up to 6 power domains

   

Route any digital or analog peripheral to any GPIO

   

1.2-V to 5.5-V interface voltages, up to four power domains

   

With reality: 

   

powering the core efficienly @ 1.8V limits the 6 power domains to <=1.8V. 

   

Opamps, DACs, REF bypass caps, have specific IO pins and using an opamp seems to mandate use of the IO pins.

   

Chris

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ETRO_SSN583
Level 9
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Thank you all.  I've been all over the datasheet - and was just hoping that there

   

was a way to reconcile page 1 features : Voltage range: 1.71 to 5.5 V, up to 6

   

power domains

   

 

   

To be precise one would need a table of conditions for the power domains.

   

 

   

Route any digital or analog peripheral to any GPIO

   

 

   

Thats true in the whole, but there is preferred routes for analog stuff due to path

   

resistance. There is an ohmmeter tool in Creator to aid users in optimizing

   

designs.

   

 

   

 using an opamp seems to mandate use of the IO pins.
 

   

No, you can route internal only an OpAmp to an A/D for example.

   

 

   

Some useful references -

   

 

   

http://www.cypress.com/?rID=39157&source=an61290     AN54181 - Getting Started with PSoC 3

   

http://www.cypress.com/documentation/application-notes/an77759-getting-started-psoc-5lp     AN77759 - Getting Started with PSoC® 5LP

   

http://www.cypress.com/?rID=39677     AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations

   

http://www.cypress.com/?rID=40247     AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations

   

http://www.cypress.com/?rID=39974     AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs

   

http://www.cypress.com/?id=4&rID=49491     Power measurements for low power modes of PSoC 3/5 on CY8CKIT-001

   

 

   

Regards, Dana.

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